Novel Processes for SOI-based mems at VTT

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NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT

James Dekker, ack. Jaakko Saarilahti, Jyrki Kiihimäki, Hannu Kattelus

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

OUTLINE

• Introduction

• Ultrasonic transducers from polysilicon

• The Plug-Up process

• SOI Resonators

• variations

• Amorphous metals

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

INTRODUCTION

• Different micromachining technologies:

• Surface Micromachining

• polysilicon and metal layers

• oxide as sacrificial layer

• Example:Acoustic emission sensor

• Bulk Micromachining

• anisotropic etching (TMAH)

• SOI-based Micromachining

• ICP etching

• Buried oxide sacrificial layer

• Example :Resonators

Both surface and SOI processes benefit from a novel release etch procedure used at VTT

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

CAPACITIVE MICROMACHINED ULTRASONIC TRANSUCER

(CMUT)

• A device for detecting ultrasonic pressure waves (6 to 13 MHz)

• NDT and ultrasonic imaging

• Surface micromachined using polysilicon

• Fully functional 500 element

CMUT matrix has been demonstrated (1 mm2)

• A Novel method for etching of the sacrificial layer has been used.

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

CMUT PROCESS

BEGIN

• Process begins with

LTO+poly + 600 nm

TEOS depositions

• Deposition and patterning of nitride

• Deposition of porous poly-Si

• Cavity formed by HF etch and SC drying, then sealed with poly Si

• More depositions and patterning to get final structure

5. Silicon nitride deposition 200 nm

6. Silicon nitride patterning

7. Polysilicon deposition

8. Cavity etching and sublimation

9. Polysilicon deposition 300 nm

13. Al –metallization patterning

END

Al -metal

Polysilicon

Silicon nitride

Polysilicon

Silicon oxide

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

RELEASE ETCHING OF THE CMUT MEMBRANE

Removing the sacrificial oxide with HF

Al -metal

Polysilicon

Silicon nitride

Polysilicon

Silicon oxide

D = 40 - 60 um

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

CHARACTERIZATION OF RESONANCE

Resonance C_15_A3

Osc Level=1 V pp DC Bias = 40 V

2.00E+03

1.60E+03

1.20E+03

0.00

-20.00

-40.00

8.00E+02

4.00E+02

-60.00

-80.00

0.00E+00 -100.00

6.50E+06 7.00E+06 7.50E+06 8.00E+06 8.50E+06

Frequency [Hz]

1.50E+07

1.30E+07

1.10E+07

9.00E+06

• Q= 100

• PULL-IN VOLTAGE ~40-200 V

Resonance frequency

C15 Gap = 600 nm

A -type

D -type

E -type

7.00E+06

5.00E+06

400000 500000 600000 700000

Effective mass 1/SQRT(m)

800000

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

LAME AND BAW RESONATORS from SOI

• Resonators for RF applications require high Q values with low power consumption.

• Low phase noise (Quartz resonators are ~-150 dBc/Hz)

• Bulk acoustic mode offers excellent characteristics compared to flexural mode

• 12 MHz BAW

• 13 MHz Lame

• gap=1 um (mask) by ICP

~400 um

BAW

LAMÉ

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

RESONATOR PROCESSING

• All MEMS processing is CMOS compatible

• 5-10 um SOI, 1 um BOX

• pattern metal

• ICP etch resonator and gaps

• HF release etch

• Supercritical drying

• Non-IC processing (esp. metals) done at back-end frequency

111 kHz

12 MHz type

Cantilever

BAM

Q (vacuum)

1.6 MHz bridge (c-c) 30000

14 MHz bridge (c-c) 1500

3000

5

2x10

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

CHARACTERIZATION

3.0

2.5

2.0

1.5

1.0

100 Hz

0.5

11.7479

11.7480

11.7481

11.7482

11.7483

f (MHz)

6

11.7 MHz BAW

4

2

0

-2

-4 Q=180 000

-6

11.7479

11.7480

11.7481

11.7482

11.7483

f (MHz)

• Measurement of S-parameters and resonance frequencies

• Phase noise (-115 dBc/Hz at 1 kHz offset)

6

13.1 MHz Lame

4

2

0

-2

-4

Q>100 000

-6

13.0952

13.0953

13.0954

13.0955

13.0956

f (MHz)

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

ALTERNATIVE SOI-PROCESS FOR RELEASING LARGE

STRUCTURES

Conventional process

Plug-Up process

Pattern and etch release holes, strip, line with poly

Nitride

Etch cavity in HF and SC Dry

Thin

Poly-Si

Fill with poly, etchback, repattern, etch gaps to release structure

Poly-Si • Gaps and release holes by

ICP etching

• Structure released by HF etch followed by SC drying

• suitable for small or rigid structures

Better yield for large structures

No holes in structure

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

MEMS, Amorphous Metals, and IC integration

MEMS first?

IC first?

Metallurgy!

Topography!

Complexity!

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

DC

Reactive co-Sputtering of Mo-Si-N

C:

Mo

34

Si

20

N

41

5.3 g/cm 3

0.75 m

W cm

(O

5

)

N

B:

Mo

19

Si

26

N

49

4.2 g/cm 3

4.8 m

W cm

(O

6

)

Shutter

Ar

Wafers

N

2 Target

MoN

Mo

2

N

-Mo-N

Mo

A

C

Mo

3

Si Mo

5

Si

3

B

MoSi

2

Si

3

N

4

Si

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Thermal Stability

200 nm Mo-Si-N layers

80

60

RT

800

900

1000

500

600

700

40 as-deposited

20

1100

Dark-Field

0

20 40 60 80 100 120 140 160 180 200 o

Temperature ( C)

1000C / 1min in Ar

Conductive

MoN or MoSi precipitates ?

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Microelectromechanical test device: variable capacitor

• Sputter MoSiN onto resist

• Dice

• O2 plasma “release etch”

Photoresist

O + O +

O +

O +

O +

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0 2 4 6

Varactor CV Curve

8 10

Voltage (V)

12 14 16 18 20

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Conclusions

- Amorphous metallic alloys are interesting alternatives for silicon in fabricating MEMS devices

- Polymeric materials can be used for sacrificial layers

- Stress is more uniform and controllable than for polycrystalline metals

- Mo-Si-N is an IC-compatible material candidate

- Low deposition temperature (down to room temperature)

- High thermal stability

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

Summary

- Surface and SOI-based micromachining are dominant processes at VTT

- New release technology facilitates the fabrication of complex structures

- Amorphous metallic alloys are interesting alternatives for silicon in fabricating MEMS devices

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