Optimizing I/O Timing Using the LogicLock
Methodology in the Quartus II Software v1.1
Technical Brief 74
October 2001, ver. 2.0
Introduction
™
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This technical brief describes how the use of the LogicLock methodology, available in
®
the Quartus II software v1.1, helps meet the input/output (I/O) performance
requirements of a design for APEXTM 20K, APEX 20KC, APEX 20KE, and APEX II
devices. This performance is achieved through the use of LogicLock timing and
placement constraints, together with the Optimize I/O cell register placement for timing
compiler setting in the Quartus II software v1.1.
Recommendations for Optimizing I/O Timing
Apply the constraints for I/O timing and logic assignments such as Fast Input Register
and Fast Output Register at the top level of the design hierarchy to affect register
placement for I/O timing. Altera suggests creating the LogicLock constraints intended
to work with the I/O timing constraints at the top-level of the design hierarchy. Altera
also recommends that pin location assignments are made to the design in order to use
the LogicLock constraints for I/O timing.
If an entity containing or feeding pins is assigned directly to a LogicLock region, the
fitter in the Quartus II software ignores the LogicLock region placement for the pins.
Hence, the LogicLock region assignments do not support locking down pin
assignments from the hierarchy.
However, if a pin is explicitly assigned to a LogicLock region, the fitter honors the
assignment, providing the LogicLock region is locked. In this case, the fitter attempts
to place the pin on the row or column adjacent to the LogicLock region. An example of
this explicit pin assignment is to select the pin name using the Node Finder and assign
it to a LogicLock region.
Effects of Compilation Timing Settings
The Optimize I/O cell register placement for timing compiler setting and the I/O Timing
Driven Compilation (TDC) settings — clock setup time (tsu) or clock to output delay
(tco) — affect the placement of the registers. The compiler places the registers in or close
to the I/O cell to meet the individual I/O timing requirements. The I/O cell registers
are used only if there is no logic between the register and the pin.
Altera recommends making individual rather than global I/O timing constraints, so as
to only affect the placement of the registers with difficult I/O timing requirements.
A difficult-to-meet tsu requirement, e.g., tsu <= 4 ns, results in register placement in the
I/O cell. If the I/O cell register is not available, the fitter optimizes the placement of the
cell containing the register to achieve the best possible tsu. See Figure 1.
Altera Corporation
M-TB-074-2.0
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TB 74: Optimizing I/O Timing Using the LogicLock Methodology in the Quartus II Software v1.1
Figure 1. Input Pins
A difficult-to-meet tco requirement, e.g., tco <= 6 ns, results in register placement in the
I/O cell. If the I/O cell register is not available, the fitter optimizes the placement of the
cell containing the register to achieve the best possible tco. See Figure 2.
Figure 2. Output Pins
In APEX 20K, APEX 20KC, and APEX 20KE devices, the output register is given
priority for bidirectional pins. In the case of tight tsu and tco constraints on a
bidirectional pin, e.g., tco = 6 ns and tsu = 4ns:
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■
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The output register is placed in the I/O cell.
The input register is placed in the logic array block (LAB) adjacent to the pin.
The output enable register is placed in the LAB adjacent to the pin.
If there is insufficient logic or routing available for the LAB adjacent to the pin, the
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MegaLAB adjacent to the pin is used.
In APEX II devices, all 3 registers are placed in the I/O cell. See Figure 3. If there is logic
between the register and the pin, the tsu, tco, and the minimum acceptable clock
frequency (fmax) requirements are optimized and the register placed to satisfy these
requirements.
For all of the above cases, the I/O register placement takes precedence over LogicLock
assignments to guarantee the I/O timing. However, the I/O register placement
influences the placement of the LogicLock constraints. As a result, the LogicLock
placement gravitates either toward the pins or registers, if necessary, in order to
achieve the fmax requirements while preserving the I/O performance.
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Altera Corporation
TB 74: Optimizing I/O Timing Using the LogicLock Methodology in the Quartus II Software v1.1
This behavior applies to all LogicLock floating location assignments, i.e., auto-size
constraints and non-locked fixed size constraints with or without back-annotation.
Fixed size, fixed location LogicLock constraints do not have the flexibility to move
toward the pin or I/O register.
After successfully meeting the performance requirements using the LogicLock
methodology, a LogicLock back-annotation does not back-annotate the registers placed
in the I/O cell. The assignments which led to that implementation control the I/O
register placement.
Figure 3. Bidirectional Pins
Optimizing a Lower-Level Module for I/O Timing
In some design cases, it is necessary to optimize the performance of lower-level entities
with connections to I/O pins. In order to get a true indication of the module’s
performance and to enable preservation of the performance when the module is
exported to the top-level project, it is necessary to use the I/O timing constraints
together with LogicLock constraints.
The same techniques and rules apply as described earlier in the Effects of Compilation
Timing Settings section. For this optimization to work, after exporting the module to
the top-level project, the timing constraints and logic options must be applied to the
appropriate pins in the top-level project. Also, set the Optimize I/O cell register placement
for timing to the same state used when optimizing the lower-level module.
Conclusion
Use LogicLock constraints, timing constraints, and logic options to help meet the I/O
and fmax performance requirements of designs targeting APEX 20K, APEX 20KC,
APEX20KE, and APEX II devices.
®
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Altera Corporation
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