www.ijecs.in
International Journal Of Engineering And Computer Science ISSN:2319-7242
Volume 3 Issue 3 March, 2014 Page No. 4044-4048
A 1.5V 3bit, 500MS/s LOW POWER CMOS Flash ADC
Manju Devi1 Arunkumar P Chavan2 Dr. K N Muralidhara3
manju3devi@gmail.com
arunkumarchavan4@gmail.com
knm08@rediffmail.com
ABSTRACT
The analog to digital converters play a vital role in today‟s world of electronic systems. The requirement of present applications
demands is high speed and low power analog to digital converter. Out of the available ADCs Flash ADC is most popular for its
highest conversion rate and its wide applications. In this paper, a 1.5v, 3-bit 500MS/s CMOS flash ADC is presented in 0.180 μm.
Improved calibration capabilities resulted in an INL and DNL smaller than 0.20 LSB with power dissipation of 2.48mw.Flash
ADC has major components like comparators, thermometer to binary encoder. The comparators are replaced by op-amp. A novel
architecture is designed for thermometer to binary encoder by using Full adders. The applications of flash ADC include data
acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives
.
Keywords
ADC (analog to digital converters), TOB (Thermometer to
Binary), FA (Full Adder), Comparator
1. Introduction
There are two basic type of converters, digital-to-analog
(DACs or D/As) and analog-to digital (ADCs or A/Ds).
Their purpose is fairly straightforward. In the case of DACs,
they output an analog voltage that is a proportion of a
reference voltage, the proportion based on the digital word
applied [1], [2]. In the case of the ADC, a digital
representation of the analog voltage that is applied to the
ADCs input is proportional to a reference voltage.
Flash analog-to-digital converters, also known as parallel
ADCs, are the fastest way to convert an analog signal to a
digital signal. Applications such as wireless communications
and digital audio and video have created need for costeffective data converters that will achieve higher speed and
resolution [3], [4]. The needs required by digital signal
processors [2] continually challenge analog designers to
improve and develop new ADC and DAC architectures.
There are many different types of architectures, each with
unique characteristics and different limitations [5].
One of the architecture which is used for converting
continuous time varying signal to digital signal is Flash
ADC [6].
2. FLASH CONVERTER
The proposed 3bit 500 MS/s ADC employs a high speed
comparators and a novel architecture of thermometric to
binary converter. The Flash ADC architecture is as shown in
Fig. 1. For an N-bit converter, the circuit employs 2N-1
comparators. A resistive-divider with 2N resistors provides
the reference voltage [8]. The reference voltage for each
comparator is one least significant bit (LSB) greater than the
reference voltage for the comparator immediately below it.
Each comparator produces a output „1‟ when its analog
input voltage is higher than the reference voltage applied to
it. Otherwise, the comparator output is „0‟. The outputs of
comparators form a thermometer code (TC) which is a
combination of a series of zeros and a series of ones. This
architecture is known as thermometer code encoding. This
name is used because the design is similar to a mercury
thermometer, in which the mercury column always rises to
the appropriate temperature and no mercury is present above
that temperature. The thermometer code is then decoded to
the appropriate digital output code.
For 3-bit flash ADC we have 7 comparators (23-1),
Thermometer to Binary Encoder and output of 3-bits.
Manju Devi1, IJECS Volume 3. Issue 3 March, 2014 Page No.4043-4048
Page 4044
Table no 1
Fig1: Flash ADC architecture
2.1 Comparator
The comparators are typically a cascade of wideband lowgain stages [9]. They are low gain because at high
frequencies it is difficult to obtain both wide bandwidth and
high gain. In this paper, comparator is designed using o-amp
which gives high gain and bandwidth. CMOS op-amp is
ubiquitous integral parts in various analog and mixed-signal
circuits and systems [10]. Two stage op-amps is designed
the first stage of the op-amp gives high gain of 60.97dB and
the second stage of the op-amp gives high output swing. The
op-amp is shown in the figure 2 below. This op-amp is a
widely used general purpose op-amp; it finds applications in
switched capacitor filters, analog to digital converters, and
sensing circuits [11].
The full adders used are designed using DPL logic [12],
[13]. The truth table of Full-adder are as shown in
table.1.From the truth table, it is observed that the output
sum So is equal to
when C=0,and the output sum So is
equal to
when C=1.Thus, a multiplexer can be
designed by considering C as selection. In the same way
when we look at the carry output CO, it is equal to A
when C=0 and carry output CO is A
when C=1. So for
carry output also, we can design a multiplexer considering C
as selection. Therefore using two multiplexer which is
driven by C, we can generate the o/p for sum and carry as
shown in the structure below in figure 3.
Fig 3: Full Adder Structure
Fig2: Op-Amp Designs
2.2 Thermometer to Binary code converter
The thermometer to binary encoder are basically constructed
using logic gates which causes more propagation delay and
also ROM Encoder are present where more number of
transistors are used[12].
A novel architecture of 7:3 encoders for conversion of
thermometer code to binary code is designed using full
adders as the basic elements. The truth table for full adder is
given below
The main advantage of this logic structure is that we do not
have separate signals for the selection of the multiplexer, the
input signal C, exhibiting a full voltage swing and no extra
delay is used to drive the multiplexers, and this reduces the
overall propagation delays. The structures of full adder have
been designed using double pass- transistor logic (DPL)
[17].
These full adders are used for designing thermometer code
to binary code converter. The outputs from seven
comparators are given to thermometer to binary code
converter for 3-bit binary encoding as shown above in figure
5.
Manju Devi1, IJECS Volume 3. Issue 3 March, 2014 Page No.4043-4048
Page 4045
Fig: Thermometer code to binary code converter
The first three most significant bits (MSBs), T6, T5, T4
from comparators are given to full adder FA-1.The next
three significant bits T3, T2, T1 are given to full adder
circuit FA-2 and the least significant bit is given to FA4.The sum bit produced by FA-1 and FA-2 are connected as
input to FA-4 .The carry bit produced by FA-1 and FA-2
and FA-4 are connected as input to FA-3. The sum bit from
FA-4 along with sum and carry from FA-3 is taken as the 3bit digital output from the ADC. The truth table for 3-bit
encoder is as shown in Table 2.
The op-amp designed here has the following results for the
given parameters as shown in Table 3.
Table 3: Op-Amp Results
3.2 Sample and hold output
Using the above op-amp, sample and hold circuits and
simulation result is as shown in figure 8 and figure 9 below
and has the sampling rate of sample and hold circuit is
500MS/s.
Table 2 Truth table for 3 bit encoder
3. SIMULATION RESULTS
3.1 OP-AMP OUTPUT
The schematic of op-amp using 180nm is shown below
Figure 8 Sample and Hold Circuits
The gain and phase plot is shown in fig:
Manju Devi1, IJECS Volume 3. Issue 3 March, 2014 Page No.4043-4048
Page 4046
Fig 9 Sample and Hold Circuit Output
3.3 Flash ADC output
The schematic of 3 bit flash adc architecture and the
simulation output is shown in figure and figure
4. Conclusion
The proposed design for a 1.5v, 3-bit CMOS flash ADC is
designed and obtained INL IS 0.2LSB; DNL IS 0.22LSB
with low power dissipation of 2.48mw and sampling rate of
500MS/s is designed. The thermometer to binary encoder
which is the major component of Flash ADC is designed
using full adder where full adder is done using DPL logic.
Future scope the designed 3-bit Flash ADC can be used in
the implementation of pipelined ADC.
5. References
[1] P. E. Allen and D. R. Holberg. “CMOS Analog Circuit
Design” second edition oxford university press. ISBN 019
5116 445, 2002.
Fig: 3 bit Flash ADC
[2] Amol Inamdar, Anubhav Sahu, Jie Ren, Aniruddha
Dayalu, and Deepnarayan Gupta, “Flash ADC Comparators
and Techniques for their Evaluation”, IEEE Transactions on
Applied Superconductivity, Vol.23, no.3, ISSN No.10518223,pp. 1-8, Jan 2013.
[3] R. Jacob Baker “CMOS: Mixed Signal Circuit Design”,
Second Edition, Wiley-IEEE Press, ISBN 978 0470-290262, 2009.
[4] N. Weste and K. Eshraghian, Principles of CMOS VLSI
Design, A System Perspective. Reading, MA: AddisonWesley, 1988.
Fig: Output of 3 bit Flash ADC
Table 4 compares these figures with the state of the art [7, 8,
16, 17–88]. To the authors‟ knowledge, this design achieves
the lowest power for flash ADCs in this technology node.
Table 4: Comparison of Analog to Digital converter
[5]
P.Iyappan, P.Jamuna and S.Vijayasamundiswary,
“Design of Analog to Digital Converter Using CMOS
Logic”, IEEE International Conference on Advances in
Recent Technologies in Communication and Computing,
ISBN no. 978-0-7695-3845-7, pp. 74-76, 2009.
[6] Channakka Lakkannavar, Shrikanth K, Kalmeshwar.N,
(2012)” Design implementation and analysis of Flash ADC
architecture with differential amplifier as comparator using
CD approach”, International Journal of Electronics Signals
and Systems (IJESS) ISSN: 2231- 5969, Vol-1 Iss-3.
[7] Nuzzo, P., et al.: „A 10.6 mW/0.8 pJ power-scalable 1
GS/s 4b ADC in 0.18 mm CMOS with 5.8 Ghz ERBW‟.
Proc. 43rd Design Automation Conf. (DAC), San Francisco,
CA, July 2006, pp. 873–878
Manju Devi1, IJECS Volume 3. Issue 3 March, 2014 Page No.4043-4048
Page 4047
[8] Sudakar S. Chauhan, S. Manabala, S.C. Bose and R.
Chandel, “A New Approach To Design Low Power CMOS
Flash A/D Converter”, International Journal of VLSI design
& Communication Systems(VLSICS),Vol.2,no.2,pp.10108,June 2011.
[9] Meghana Kulkarni, V. Sridhar, G.H. Kulkarni,“4-Bit
Flash Analog to Digital Converter Design using CMOSLTE Comparator”, IEEE Asia Pacific Conference on
Circuits and Systems (APCCAS) ,ISBN no. 978-1-42447456-1, pp.772-775, Oct.2010.
[10] P.Rajeswari, R.Ramesh, A.R.Ashwatha 2012,” An
approach to design Flash Analog to Digital Converter for
High Speed and Low power Applications”, International
Journal of VLSI design & Communication Systems
(VLSICS) Vol.3, No.2.
[11] Rahul Moud,D.B.Ojha, 2012” Design of Chip for
Flash ADC application of MCML in 180nm Technology”,
Journal of Computing Technologies ISSN 2278 –
3814,volume1.
[12] Erik Sall and Mark Vesterbacka, “Thermometer-toBinary Decoders for Flash Analog-to-Digital Converters”,
European Conference on Circuit Theory and Design ECCTD,ISBN no.1-4244-1342-7, pp. 240-243, July2007.
[13] M Suresh, Santoshi Sahu, Kiran Sadangi and A K
Panda 2009,” A Novel Flash Analog-to-Digital Converter
Design using Cadence Tool”, 978-0-7695-3845-7/09 IEEE
computer society
[14] Sudakar S. Chauhan, S. Manabala, S.C. Bose and R.
Chandel, “A New Approach To Design Low Power CMOS
Flash A/D Converter”, International Journal of VLSI design
& Communication Systems(VLSICS),Vol.2,no.2,pp.10108,June 2011.
[15] Ferragina, V.; Ghittori, N.; Maloberti, F., “Low-power
6-bit flash ADC for high-speed data converters
architectures”, IEEE International Symposium on circuits
and Systems (ISCAS), Print ISBN: 0-7803-9389-9, pp.
3930-3933, Sep- 2006.
Prof. Manju Devi
Born on 10th Dec 1974 in Uttar Pradesh, obtained
her B.E degree in Electronics and Communication
Engineering from Anna University, Chennai and M.Tech
degree in Applied Electronics from Visvesvaraya
Technological University (VTU), Karnataka. At present
working as an Associate Professor in the department of ECE
at BTLIT, B‟lore. Almost sixteen years of teaching
experience in engineering colleges. Her areas of interest are
VLSI design, analog and mixed mode VLSI design and
digital electronics. She is pursuing her Ph.D degree from
VTU in the field of analog and mixed mode VLSI.
Prof. Arunkumar P Chavan
born on July, 4th, 1987 in Karnataka, India,
obtained his B.E degree in Electronics and Communication
Engineering from Visvesvaraya Technological University
(VTU), Belgaum and M.Tech degree in VLSI Design and
Embedded system from Visvesvaraya Technological
University (VTU), , India. He is working as an Assistant
Professor at RV College of Engineering. His areas of
interest are VLSI design, Analog circuit design and digital
electronics.
Dr K.N.Muralidhara:
[16] Banik, S., Gangopadhyay, D., and Bhattacharyya, T.K.:
„A low power 1.8 V 4-bit 400-MHz Flash ADC in 0.18 m
digital CMOS‟. Proc. VLSID, Hyderabad, India, January
2006, p. 6
[17] Wu, L., Huang, F., Gao, Y., Wang, Y., and Cheng, J.:
„A 42 mW 2 GS/s 4-bit flash ADC in 0.18-mm CMOS‟. Int.
Conf on WCSP, Nanjing, People‟s Republic of China,
November 2009, pp. 1–5
[18] G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. Van der Plas
andJ. Vandewege, Low-power 4-bit flash analogue to digital
converter for ranging applications ELECTRONICS
LETTERS 6th January 2011 Vol. 47 No. 1.
Obtained his B.E.degree in E&C Engg from PES college
of Engg , Mandya during 1981, ME during 1987from and
Ph.D during 2002 from University of Roorkee. His field of
interest is on semiconductor devices and presently working
as professor and Head of the Dept. He is guiding 5
candidates for Ph.D program and actively participated in all
the developmental activities of the college. He has about 35
publications to his credit.
Manju Devi1, IJECS Volume 3. Issue 3 March, 2014 Page No.4043-4048
Page 4048