Lab 2 Revisited Exercise
+15V
1K
100k
• Wire up led display
• Note the ground leads
• LED orientation
2N2222
6.091 IAP 2008 Lecture 3
1
Comparator, Oscillator
+5
+15
2
1k
V-
7
3
Vin
V+
4
6
Vo
Notice that power connections are
shown; bypass capacitors included
for power supply filtering.
All voltage measurements are
referenced to ground
6.091 IAP 2008 Lecture 3
2
Op-Amps
Inverting Amplifier
Integrator
Null Adjustment
C
10k
R2
R1
1k
R1
Vin
V-
V-
V-
Vin
Vin
Vo
V+
5
Vo
V+
Vo
V+
1
10k
-15V
R2
vo = −
vin
R1
vo = −
vin
dt
∫
RC
For clarity, power connections and bypass
capacitors not shown.
6.091 IAP 2008 Lecture 3
3
Lab Exercise - Schmitt Trigger
•
Schmitt trigger have
different triggers
points for rising edge
and falling edge.
•
Can be used to
reduce false triggering
•
This is NOT a
negative feedback
circuit.
V-
Vin
Vo
V+
R2
R1
6.091 IAP 2008 Lecture 3
4
Notes
• IC power supply
connections generally
not drawn. All
integrated circuits
need power!
• Use standard color
coded wires to avoid
confusion.
6.091 IAP 2008 Lecture 3
Potentiometer
internals
5
Power Supplies, Voltage Regulators
3 terminal
regulator
• Conventional Power
Supply
– rectify (convert AC to
DC)
– filter out the ripple
– regulate the voltage
.
• 3 terminal IC
regulator
6.091 IAP 2008 Lecture 3
6
Wire Gauge
• Wire gauge: diameter is inversely
proportional to the wire gauge number.
Diameter increases as the wire gauge
decreases. 2, 1, 0, 00, 000(3/0) up to 7/0.
• Resistance
– 22 gauge .0254 in 16 ohm/1000 feet
– 12 gauge .08 in 1.5 ohm/1000 feet
– High voltage AC used to reduce loss
6.091 IAP 2008 Lecture 3
7
78XX Voltage Regulator
+5V, +12V, +15V
-5V, -12V, -15V
Reprinted with permission of National Semiconductor Corporation.
6.091 IAP 2008 Lecture 3
8
7805 Circuit
Reprinted with permission of National Semiconductor Corporation.
6.091 IAP 2008 Lecture 3
9
Zener Diode
4.7k
• Zener diodes will maintain a
fixed voltage by breaking down
at a predefined voltage (zener
voltage).
Lab exercise
• Wire up the above circuit with a 1N752A (5.6V)
zener.
• Set the FG for a 0-10V ramp. Display the
output of the FG and the voltage across the
zener on the oscilloscope. Describe what is
happening.
6.091 IAP 2008 Lecture 3
10
Adjustable Voltage Source
+15V
270Ω
1N758
0.1uf
10K
V+
10v
Vo
V-
6.091 IAP 2008 Lecture 3
11
Adjustable Voltage Power Supply
+15V
270Ω
1N758
Vo
0.1uf
1uf
10K
V+
10v
V-
.
6.091 IAP 2008 Lecture 3
12
LM317 Three Terminator
Adjustable Voltage Regulator
Reprinted with permission of National Semiconductor Corporation.
•
•
•
•
First 3 terminal adjustable voltage regulator
1.2 - 25 Voltage output range
Short circuit protected
Thermal shutdown
6.091 IAP 2008 Lecture 3
13
LM317
Reprinted with permission of National Semiconductor Corporation.
6.091 IAP 2008 Lecture 3
14
Buck Converters
• Linear power supplies
are very inefficient
• Power dissipated by
regulating element
• Buck converters
operating in switching
mode (on/off)
6.091 IAP 2008 Lecture 3
+
.
15
555 Timers
• Simple, versatile, low
cost IC for timing
applications: oscillators,
one-shot pulse
generator, pulse width
modulator, missing
pulse detector
• Circuit: two
comparators, flip flop,
resistor divider and a
discharge transistor.
VCC
8
ready
6.091 IAP 2008 Lecture 3
Threshold 6
Control Voltage
5k
5
R Flip
+
Inhibit/
S Reset
5k
Trigger
7
+
Comp
_A
2
Flop
Q
Comp
_B
Discharge
3
Output
5k
1
Gnd
4
Reset
Figure by MIT OpenCourseWare.
16
555 Block Diagram
VCC
8
ready
Threshold 6
Control Voltage
5k
7
+
Comp
_A
5
5k
Q
Inhibit/
S Reset
+
Trigger
Comp
_B
2
Discharge
R Flip
Flop
3
Output
5k
4
Reset
1
Gnd
Figure by MIT OpenCourseWare.
6.091 IAP 2008 Lecture 3
S
R
Reset
Output
1
1
1
last state
0
1
1
low
1
0
1
high
0
0
1
high
NA
NA
0
low
17
RC Equation
Vs = 5 V
Vs = 5 V
Switch is closed t<0
Switch opens t>0
R
Vs = VR + VC
Vc
C
Vs = iR R+ Vc
Vs =
t
−
⎛
⎞
RC
Vc = 5⎜⎜1 − e ⎟⎟
⎝
⎠
6.091 IAP 2008 Lecture 3
iR = C dVc
dV
RC c + Vc
dt
dt
t
−
⎛
⎞
RC
Vc = Vs ⎜⎜1 − e ⎟⎟
⎝
⎠
18
Monostable Circuit
VCC
Ra
555 or 1/2 556
Discharge
R
Control voltage
Comp
Threshold
C
R
Flip flop
Output
Output
Comp
Trigger
R
Reset
Figure by MIT OpenCourseWare,
based on Philips Semiconductors datasheet.
6.091 IAP 2008 Lecture 3
Reprinted with permission of National Semiconductor Corporation.
19
Oscillator (Astable)
VCC
Rb
RA
Discharge
7
5
Control voltage
8
555
R
Comp
Threshold
6
R
Flip flop
Output
3
Comp
Trigger
2
R
C
1
4
Reset
Figure by MIT OpenCourseWare,
based on Philips Semiconductors datasheet.
6.091 IAP 2008 Lecture 3
Reprinted with permission of National Semiconductor Corporation.
20
Closet Light Timer – Lab Exercise
+15
+15
8
+15
R
reset
1k
10k
555
output
threshold
trigger
1k
discharge
C
control
0.1uf
1
0.01
uf
ton = 1.1RC
Switch closed = door closed
6.091 IAP 2008 Lecture 3
21
Lab Exercise
•
•
•
•
•
Wire up zener diode circuit
Build variable voltage power supply
Build variable current source
Build 555 oscillator
Build closet light timer
6.091 IAP 2008 Lecture 3
22
Analog Circuit Summary
•
•
•
•
3 Terminal Regulators
Zener Diodes
Power Supplies
555 Timers & circuits
6.091 IAP 2008 Lecture 3
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Important Missing Links
• The real world is an analog world.
However, computing is best performed via
digital systems (i.e. the processing of data
with 0’s and 1’s).
• Digital-Analog Conversion
• Analog-Digital Conversion
6.091 IAP 2008 Lecture 3
24
Analog vs Digital
• Analog systems/devices work with
information in a continuous stream: clock
with hands, mercury thermometer, vinyl
records, analog meters, calipers.
• Digital systems/devices work with
information in a discontinuous stream
(0,1): digital thermometer, digital meters,
computers.
6.091 IAP 2008 Lecture 3
25
Music – An Example
• CD’s are digital systems that sample and stores
audio data
– sampling rate: 44.1 khz
– data stored in 16 bit format; implies
216 = 65,536 possible output levels
• DVD Audio samples at 96-192kHz/24 bits
• Analog records have an infinite number of output
levels.
6.091 IAP 2008 Lecture 3
26
D-A Conversion (DAC)
•
Problem: take a digital signal and convert to an analog voltage: R-2R ladder
0001 -> 1/16 * 5 volt
0010 -> 2/16 * 5 volt
0011 -> 3/16 * 5 volt
...
1101 -> 14/16 * 5 volt
1111 -> 15/16 * 5 volt
•
Note that the outputs are at discrete levels – not continuous!
R
R
R
1⎡
1
1
1
⎤
B3 + B2 + 2 B1 + 3 B0 ⎥
⎢
2⎣
2
2
2
⎦
R
5
Vo
R
2R
2R
+5
+5
Bo
6.091 IAP 2008 Lecture 3
2R
B1
2R
+5
B2
+5
B3
27
Digital Circuits
• Real world analog signals have noise – unavoidable.
• Digital circuits offers better noise immunity.
• Use voltage to represent “0” and “1”
– Avoid forbidden voltage zone.
– Make standards tighter for output than for inputs.
• Data (HCMOS family): 0 (low), 1 (high)
– Input voltage low: 0.0 – 0.7v
– Input voltage high: >2.0V
– Output low: <0.4v
– Output high: >3.98v
6.091 IAP 2008 Lecture 3
28
Digital Circuits
+5V
HCMOS 1 (high)
– Output high: >3.98v
– Input voltage high: >2.0V
output high
range
+3.98V
input high
range
noise
margin
+2.0V
Forbidden Zone
HCMOS 0 (low)
– Output low: <0.4v
– Input voltage
low: 0.0 – 0.7v
6.091 IAP 2008 Lecture 3
0.7V
noise
margin
0.4V
input low
rage
output low
range
.
29
Power Requirements
• The following power supplies are common for analog
and digital circuits:
+5v for digital circuits,
+15v, -15v for analog,
-5v, +12v, -12v also used
• Other voltages generally derived.
6.091 IAP 2008 Lecture 3
30
Boolean Algebra
A B = A & B
A
= Inverse of A
A B = Inverse of [A&B]
DeMorgan's Law
A B
= A + B
A + B = A & B
6.091 IAP 2008 Lecture 3
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Digital System Implementation
• Start with AND, OR, NOR, NAND gates and
add more complex building blocks: registers,
counters, shift registers, multiplexers. Wire
up design. High manufacturing cost, low fix
costs. Examples 74LS, 74HC series IC
• For volume production, move to PALs,
FPGAs, ASICs. Low manufacturing cost,
high fix costs.
6.091 IAP 2008 Lecture 3
32
Basic Gates
Circle
indicates
inversion
6.091 IAP 2008 Lecture 3
33
74LS00 NAND Gate
Dual-In-Line Package
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
This device contains four independent gates each
of which performs the logic NAND function.
Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS00 datasheet.
6.091 IAP 2008 Lecture 3
34
74LS02 NOR Gate
Dual-In-Line Package
VCC
Y4
B4
A4
Y3
B3
A3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Y1
A1
B1
Y2
A2
B2
GND
This device contains four independent gates each
of which performs the logic NOR function.
Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS02 datasheet.
6.091 IAP 2008 Lecture 3
35
74LS08 AND Gate
Dual-In-Line Package
VCC B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
This device contains four independent gates each
of which performs the logic AND function.
Figure by MIT OpenCourseWare, adapted from the National Semiconductor 54LS08 datasheet.
6.091 IAP 2008 Lecture 3
36
Building Logic
• From basic gates, we
can build other
functions: Exclusive
OR Gate
X
Z
Y
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
0
X
Y
6.091 IAP 2008 Lecture 3
Z
37
74LS86 Exclusive OR
VCC
14
13
12
11
10
9
8
1
2
3
4
5
6
7
GND
Truth Table
In
Out
A
B
Z
L
L
L
L
H
H
H
L
H
H
H
L
Figure by MIT OpenCourseWare, based on Motorola datasheet.
6.091 IAP 2008 Lecture 3
38