Design for Test of Digital Systems
TDDC33
Lab 4
Boundary Scan in Action
Date of last revision 21/08/2009
2009
Dimitar Nikolov IDA/SaS ESLAB
TDDC33 Design for Test of Digital Systems
Table of Contents
Table of Contents........................................................................................................................................2
1.Introduction..............................................................................................................................................3
1.1.Input..................................................................................................................................................3
2.Assignment 1: Improving Boundary Scan fault coverage..........................................................................3
3.Assignment 2: Running tests for diagnosing potential faults on the board..............................................3
4.Examination and submission....................................................................................................................4
4.1.Oral examination...............................................................................................................................4
4.2.Written examination..........................................................................................................................4
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1. Introduction
The goal of this lab is to get experience and knowledge about board testing using the Boundary
Scan IEEE 1149.1 standard.
The following aspects will be covered:
• Improving Boundary Scan fault coverage
• Running tests to diagnose potential faults on the board
The following tools will be used:
• TSTAP Studio1
1.1. Input
A netlist file demo.nod, BSDL file 9320_84.bsd, and boundary scan model file 8244.bmo are
all the files that you will need to solve this lab.
You can download these files using the following link:
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www.ida.liu.se/~TDDC33/labs/download/lab4.zip
2. Assignment 1: Improving Boundary Scan fault coverage
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Create new TSTAP project, importing the necessary files
Run the TSTAP-PG tool to generate the test patterns
Examine the fault coverage of the generated test patterns
Run the test using TSTAP-RT tool
Iterate through the last three steps to improve the fault coverage, such that you achieve a
fault coverage of at least 50%.
*Hints :
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using Cluster models may increase the fault coverage
flash device should not be allowed to drive nodes connected to
Boundary Scan device
3. Assignment 2: Running tests for diagnosing potential
faults on the board
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On the Demo Board, open switch 6
Run the Interconnect test
Analyze the results, and try to find what went wrong
*Hints:
-
1
in CMOS technology, a short circuit is represented with logic 1
try running different types of test on the board.
TSTAP Studio is a software provided by SAAB Aerotech
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4. Examination and submission
4.1.
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Oral examination
Prepare to show your results and to answer questions about the lab assignments during
the lab sessions. Notify the lab assistant!
4.2.
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Written examination
Write a report containing the results from Assignmet1, Assignment2 and Assignment3.
Write a short summary of your personal experience of the lab (will not be graded). This
summary can for instance contain comments on the level of difficulty, the instructions,
the tools, and possible improvements.
Place the report inside a Laboration report cover, which should be signed and submitted
to the lab assistant. (The Laboration report cover can be found by the printers.)
The deadline for submitting the lab is presented on the course web-page.
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Good Luck!
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