International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
Implementing a Low Dense 64-Bit Vedic
Multiplier Using CLA
1
.Yeletiisaacbabu , 2. G.Venkata Rao
1.M.tech, Systems & Signal Processing, Lakireddy Bali Reddy College of Engineering, Mylavaram
2. M.Tech(Ph.D), ECE, Lakireddy Bali Reddy College of Engineering, Mylavaram
ABSTRACT: The main objective of this project is to
multiplier
design an enhanced Vedic multiplier using elaborated
microprocessors, digital signal processors, and
methodologies. This project plays a vital role in many
emerging media processors [1]–[4]. It is also a kernel
industrial, telecommunication applications. Since, it
operator in appli- cation-specific data path of video
has many applications in all fields; this Vedic
and audio codecs, digital filters, computer graphics,
multiplier has to be designed with many advantages
and embedded systems [5]–[8]. Com- pared with
like power consumption, latency etc. Here, in this
many other arithmetic operations, multiplication is
project, entire 64 bit multiplier is designed with low
time-consuming and power hungry. The critical paths
density;
of
domi- nated by digital multipliers often impose a
components are required to implement this multiplier.
speed limit on the entire design. Hence, VLSI design
UrdhvaTiryagbhyam rule along with Barrel shifter is
of
used to reduce number of required components. This
dissipation, is still a popular research subject. Now a
Indian ancient Vedic mathematics rules can be
day’s all CPU units, any machinery parts utilizes a
combined with many advanced techniques provides
basic arithmetic operations like addition, subtraction,
lot of applications with more advantages.
multiplications. Each and every operation involves
implies
40 percent
less
number
is a ubiquitous arithmetic unit in
high-speed
multipliers,
with
low
energy
multiplier operation in its salvation. While there have
KEYWORDS:
Vedic mathematics, Multiplier,
been a lot of work on simple schemes for operand
UrdhvaTiryagbhyam, Pass Transistor, probability,
guarding,
Carry save addition, Computer Algebra System,
multiplcation throughput is more scarce. Achieving
black-boxes
double throughput for a multiplier is not as
work
that
simultaneously
considers
straightforward as, for example, in an adder, where
INTRODUCTION:
MULTIPLICATION
is
a
complex arithmetic operation, which is reflected in its
relatively high signal propagation delay, high power
dissipation, and large area requirement. When
choosing a multiplier for a digital system, the
bitwidth of the multiplier is required to be at least as
wide as the largest operand of the applications that
are to be executed on that digital system. THE digital
ISSN: 2231-5381
the carry chain can be cut at the appropriate place to
achieve narrow-width additions. It is of course
possible to use several multipliers, where at least two
have narrow bitwidth, and let them share the same
routing, as in the work of Loh, but such a scheme has
several drawbacks: i) The total area of the multipliers
would increase, since several multiplier units are
used. ii) The use of several multipliers increases the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
fanout of the signals that drive the inputs of the
multipliers. Higher fanout means longer delays
and/or higher power dissipation. iii) There would be a
need for multiplexers that connect the active
multiplier(s) to the result route. These multiplexers
would be in the critical path, increasing whole
latency as well as power consumption.
VEDIC MATHEMATICS:
Vedic Math essentially rests on the 16 Sutras or
mathematical formulas as referred to in the Vedas.
Sri Sathya Sai Veda Pratishtan has compiled these 16
Sutras and 13 sub-Sutras. Vedic book was first
published in 1965, Tirthaji been propagate the
methods since much earlier, through lectures and
classes.] He wrote the book in 1957 during his tour of
the United States The typescripts was returned to
India in 1960 after his death. It was published in
1965, five years after his death as 367 pages in 40
hapters. Reprints were made in 1975 and 1978 with
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
fewer typographical errors. Several reprints have
been made since the 1990s.
URDHVA TIRYAGBHYAM:
123
456
____
558
5) Now we continue with the cross multiplication, this time
This sutra, as the title of this post suggests, translates to
“Vertically and Crosswise”. This sutra is one of the best
multiplying (2 x 6) and (3 x 5). Add these two numbers
known of the Vedic Sutras, and has found many
together…12 + 15 = 27. Now lot’s of carrying-over is
application.
about to happen. We write down the ‘7’ as the fourth term,
and carry the ‘2’. We add this ‘2’ to our third term
Multiplication of two 3-Digit Numbers
(‘8′)…but this now equals ’10’. We write down ‘0’ in the
1) Write out the two numbers in the following way (or
third place, and carry the ‘1’. This makes our second term
visualize it…this may take a little work keeping track of all
‘6’ now … (5 + 1). I hope that didn’t confuse you…if it did
the numbers).
let
123
456
456
MULTIBIT PROOF:
————-
me
know
in
the
comments
1
2
3
We will represent our two numbers as the terms (ax^2 + bx
2) Since I’ll be working from left to right, the first thing we
will do is multiply the left-hand side vertically. 1 x 4 =
+ c) and (dx^2 + ex + f), where x = 10, and the other
variables are numbers between 1 and 9.
4….write ‘4’ down.
123
For this first step, the right-hand side of the equation
456
continues on the second line…formatting errors are
————-
preventing me from writing it neater (Sorry!). So please
4
bear with me, while I attempt to make it somewhat
3) Next we will cross multiply and add. (1 x 5) + (4 x 2) =
readable.
13. Since we can only keep one digit, we keep the ‘3’ and
carry the ‘1’. Now the first term becomes ‘5’…(4+1).
123
(ax^2 + bx + c) * (dx^2 + ex + f) = (ad)*(x^4) + (ae)*(x^3)
+ (af)*(x^2) + (bd)*(x^3) + (be)*(x^2) + (bf)(x) +
(cd)*(x^2) + (ce)(x) + cf
456
(ax^2 + bx + c) * (dx^2 + ex + f) = (ad)(x^4) + (ae +
————-
bd)(x^3) + (af + be + cd)(x^2) + (bf + ce)(x) + cf
53
It ends up looking like this…
4) This is the new step. We are going to cross
multiply (1 x 6) and (4 x 3), and multiply the middle
term vertically (2 x 5). Add these three numbers
together…6 + 12 + 10 = 28. We put down the ‘8’,
and carry the ‘2’ over. Thesecond term now becomes
‘5’…(3 + 2).
ISSN: 2231-5381
abc
def
—————
(ad)(x^4) + (ae + bd)(x^3) + (af + be + cd)(x^2) + (bf +
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International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
MULTIPLIER ARCHITECTURE:
ce)(x) + cf
Or if all those exponents and extra addition signs make
things confusing for you…here’s another way to look at it.
Split the answer up into 5 different parts, which are show
below separated by ‘|’ sign’s.
abc
def
—————
(ad) | (ae + bd) | (af + be + cd) | (bf + ce) | (cf)
To figure out how many parts its going to ultimately need
to be split up into you can just use this simple formula…
n + (n-1)
where ‘n’ equals the number of digits of the larger number.
The 2X2 Vedic multiplier module is implemented
For instance 123 has ‘3’ digits…so 3 + (3-1) = 3 + 2 = 5.
using four input AND gates & two half adders which
Say your multiplying 456 x 3…how many digits? Three
is displayed in its block diagram in Fig. 3. It is found
that the hardware architecture of 2x2 bit Vedic
agai
multiplier is same as the
5607
hardware architecture of
2x2 bit conv entional Array Multiplier \[2]. Hence it
6) And finally we multiply the right-hand side vertically. (3
is concluded that multiplication of 2
bit binary
x 6) = 18. We write down the ‘8’, and carry the ‘1’. Add
numbers by Vedic method does not made efficiency.
the ‘1’ to our fourth term (‘7′) to give us ‘8’, write that
Very precisely we can state that the total delay is
down in the fourth spot.
only 2 halfadder delays, after final bit products are
123
generated, which is very similar to Array multiplier.
456
So we switch over to the implementation of 4x4 bit
————56088
Vedic multiplier which uses the 2x2 bit multiplier as
a basic building block. The same method can be
extend ed for input bits 4 & 8.
Answer: 123 x 456 = 56,088
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
RESULT:
REFERENCES:
SIMULATION:
1. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K
(2005) Low-power scan design using first-level sup- ply gating.
IEEE Trans Very Large Scale Integr Syst 13(3): 384–395, Mar
2. Borkar S, et al (2003) Parameter variations and impact on circuits and microarchitecture. Design Automation Conference,pp
338–342
3. Bushnell ML, Agrawal VD (2000) Essentials of electronic
testing for digital, memory, and mixed-signal VLSI circuits.
Kluwer, Boston
4. Calhoun BH, Honore FA, Chandrakasan A (2003) Design
methodology for fine grained leakage control in MTCMOS.In:
International symposium on low power electronicsdesign, Seoul,
pp 104–107, 25–27 August
5. Cheng K-T, Devadas S, Keutzer K (1991) A partial en- hanced
scan approach to robust delay-fault test generation for sequential
circuits. In: International test conference,Nashville, pp 403–410,
26–30 October
6. DasGupta S, Eichelberger EB, Williams TW (1978) LSI chip
design for testability, digest of technical papers. In:IEEE
SYNTHESIS:
international solid-state circuits conference, IEEE,Piscataway, pp
216–217, Feb
PARAMETER
EXISTING
PROPOSED
AREA
187 um
120 um
[7]Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim and
POWER
330 mw
280 mw
Yong Beom Cho, “Multiplier design based on ancient Indian Vedic
Mathematician”, International SoC Design Conference, pp. 65- 68,
2008.
CONCLUSION: In this paper, a high-speed and
[8]Parth Mehta and Dhanashri Gawali, “Conventional versus
energy efficient VEDIC multiplier designed based on
Vedic mathematics method for Hardware implementation of a
a new covalent VEDIC encoding algorithm is
multiplier”, International conference on Advances in Computing,
Control, and Telecommunication Technologies, pp. 640-642, 2009.
presented. The idea is to polarize two adjacent
encoded digits into a differential pair to restore the
effective VEDIC partial product reduction rate
[9]Ramalatha, M.Dayalan, K D Dharani, P Priya, and S Deoborah,
“High Speed Energy Efficient ALU Design using Vedic
Multiplication Techniques”, International Conference on Advances
without the NB-to-VEDIC conversion overhead. The
In Computationa Tools for Engineering Applications (ACTEA)
proposed method fully exploits the characteristics of
IEEE, pp. 600-603, July15-17, 2009.
the positive–negative complement coding of VEDIC
[10]Sumita
Vaidya
and
Deepak
Dandekar,
“Delay-Power
number to directly generate a VEDIC partial product
Performance comparison of Multipliers in VLSI Circuit Design”,
from two adjacent encoded digits.
International Journal of Computer Networks & Communications
(IJCNC), Vol.2, No.4, pp 47-56, July 2010.
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 15 Number 1 – Sep 2014
[11]S.S.Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur
and Girish V A “Implementation of Vedic Multiplier For Digital
Signal ” International conference on VLSI communication &
instrumentation
[12]Pushpalata Verma, K. K. Mehta” Implementation of an
Efficient Multiplier based on Vedic Mathematics Using EDA
Tool” International Journal of Engineering and Advanced
Technology (IJEAT) ISSN: 2249 – 8958, Volume-1, Issue-5, June
2012
Pursuing
L.B.R.C.E,
B.Tech
from
M,tech
st'marys
from
engineering
college, chebrol , Guntur
Pursuing Ph.D from
JNTU Kakinada., M.Tech
in VLSI System Design
from "Hyderabad Institute
Of
Engineering
And
Technology", Hyderabad.,
B.Tech in Electronics and
Communication Engineering from "Nimra College
Of Engineering & Technology", Vijayawada (1998 –
2002).
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