International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
Design of Double Edge Operated Low Power Clocking
System
* Mr.Parisapogu Ravi Kumar1
1
Ms. J Deenamani2
PG Student (M. Tech), Dept. of ECE, Amrita Sai Institute of Science And Technology, Kanchikacharla, A.P.
2 Assistant Professor, Dept. of ECE, Amrita Sai Institute of Science And Technology, Kanchikacharla, A.P.
Abstract: A new family of low-power and high-performance flip-flops, namely conditional data
mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a
configuration that eliminates redundant internal transitions. We present two CDMFFs, having
differential and single-ended structures, respectively, and compare them to the state-of-the-art
flip-flops. The results indicate that both CDMFFs have the best power-delay product in their
groups, respectively. In the aspect of power dissipation, the single-ended and differential
CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less
power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of
performance, CDMFFs achieve small data-to-output delays, comparable to those of the
transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of
timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flipflops. A post-layout case study is demonstrated with comparison to a transmission-gate flipflop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and
28% less in power at 25% data activity, in spite of the 34% increase in size.
Keywords: Flip-Flop, Data Mapping, Delay Reduction, Xilinx.
system power. One idea is to reduce
1. Introduction
In
recent
system,
VLSI‟s,
a
including
clocking
clock
clock
voltage
swing,
which
was
pursued but it required four clock
interconnections and Ffip-Flops,(F/F),
lines,
consumes 20‟% to 45‟% of the total
interconnection
chip Power. This is partially because
Moreover, routing four clock lines is
the activation ratio of a clock system
disadvantageous
is unity. In this clocking system
phase adjustment is difficult. Power
power, 90% is consumed by the last
consumption is a major bottleneck of
branches of the clock distribution
system performance and is listed as
network which drive directly Flip flops
one of the top three challenges in
and the flip flops themselves. In order
International Technology Roadmap for
to achieve low-power VLSI‟s, it is
Semiconductor 2008[8].
important
to
reduce
ISSN: 2231-5381
the
which
will
increase
clock
capacitance.
in
area
and
clocking
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the
International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
In practice, a large portion of the
CDMFFs consume the least power at
on chip power is consumed by the
data activity less than 50%, and are
clock system which is made of the
31% and 26% less power than the
clock distribution network and flop-
conditional capture flip-flops at 25%
flops. In this paper, various design
data
techniques for a low power clocking
aspect
system are surveyed. Among them is
achieve small data-to-output delays,
an effective way to reduce capacity of
comparable
the clock load by minimizing number
transmission-gate pulsed latch and
of clocked transistors. To approach
the modified-sense-amplifier flip-flop.
this, we propose a novel clocked pair
In the aspect of timing reliability,
shared flip-flop which reduces the
CDMFFs have the best internal race
number of local clocked transistors by
immunity among pulse-triggered flip-
approximately 40%. A 24% reduction
flops. A post-layout case study is
of clock driving power is achieved. In
demonstrated with comparison to a
addition, low swing and double edge
transmission-gate
clocking, can be easily incorporated
results
into the new flip-flop to build clocking
CDMFF has 34% less in data-to-
systems. A new family of low-power
output delay and 28% less in power at
and
25% data activity, in spite of the 34%
high-performance
flip-flops,
namely conditional data mapping flipflops (CDMFFs), which reduce their
dynamic power by
inputs
to
a
eliminates
mapping
their
configuration
that
redundant
internal
activity,
of
respectively.
performance,
to
indicate
In
the
CDMFFs
those
of
the
flip-flop.
the
The
single-ended
increase in size.
2. Background of ET Flip Flops
Double Edge Triggering:
Using half frequency on the clock
distribution network
will
save
transitions. We present two CDMFFs,
approximately
having differential and single-ended
consumption on the clock distribution
structures, respectively, and compare
network. However the flip-flop must be
them to the state-of-the-art flip-flops.
able to be double clock edge triggered.
The
Double
clock
edge
CDMFFs have the best power-delay
reduces
the
power
product
frequency in equation [10]
results
indicate
in
their
that
both
groups,
half
of
the
power
triggering method
by
decreasing
respectively[10].
In the aspect of power dissipation,
the
single-ended
ISSN: 2231-5381
and
differential
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
Figure 1 A Gate Level D Flip Flop Design
Single edge Triggered flip flop
A single-edge triggered flip flop can
be
implemented
by
two
transparent
Figure 3 Flip Flop With Increased Transistors
latches in series, a double edge-triggered
flip flop can be implemented by two
transparent
latches
in
parallel.rtl
schematic of the flip flop is shown in the
below fig.2
Figure 4 Proposed method
Clock gating:
When a certain block is idle, we
can disable the clock signal to that block
to save power. Gated master slave flip-
Figure 2 Single Edge Triggered Flip Flop
flop was
Low Swing Voltage
Using a low swing voltage on the
proposed.
operation
and
Both
conditional
clock gating
methods
clock distribution network can reduce
reduce power by decreasing switching
the clocking power consumption since
activity[10].
power is a quadratic function of voltage.
To use low swing clock distribution, the
flip-flop should be a low swing flip- flop.
For example, low swing double-edge flipflop (LSDFF) [8] is a low swing flip-flop.
Figure 5 Proposed Clock Gating Flip Flop
For increase in the speed of the flip flop
the transistors are increased in parallel
Advantages:
Reducing Short Current Power by
as shown in the below fig.3 [10]
split
path
can
reduce
the
short
current power, since pMOS and nMOS
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
are driven by separate signals. Reducing
power of clocked nodes is important
since
clocked
node
has
100%
activity. One effective way of low power
design for clocking system is to reduce
clock
capacity
load
by
minimizing
number of clocked transistor. Any local
clock load reduction will also decrease
the global power consumption [10]
Conditional Data Mapping Flip-Flop
A large part of the on-chip power
is consumed by the clock drivers [8]. It is
desirable to have less clocked load in the
system. CDFF and CCFF in Section II
both have many clocked transistors. For
example,CCFF
used
14
clocked
transistors, and CDFF used 15 clocked
Figure 6 Conditional data Mapped Flip Flop
However, there is redundant clocking
transistors. In contrast, conditional data
capacitance
in
CDMFF.
mapping flip-flop (CDMFF, Fig.6) used
remains
or
1,
only seven clocked transistors, resulting
transistors, P1 and P2, keep switching
in about 50% reduction in the number of
without useful computation, resulting in
clocked transistors, hence CDMFF used
redundant
less power than CCFF and CDFF. (Note
necessary to reduce redundant power
that CDFF used double edge clocking.
consumption here.
0
the
clocking.
When
pre
data
charging
Clearly,
it
is
For simplicity purposes, we did not
Further, CDMFF has a floating
include the power savings by double edge
node on critical path because its first
triggering
distribution
stage is dynamic. When clock signal
network). This shows the effectiveness of
CLK transits from 0 to1, CLKDB will
reducing clocked transistor numbers to
stay
achieve
CDMFF
produces an implicit pulse window for
outperforms CCFF and CDFF in view of
evaluation. During that window, both
power consumption.
P1, P2 are off. In addition, if D
on
low
the
clock
power.
Since
1
for
a
short
while
which
transits from 0 to 1, the pull down
network will be disconnected by N3
using data mapping scheme (N6 turns
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
off N3); If D is 0, the pull down
CPSFF is proposed, which reduces local
network is disconnected from GND
clock transistor number by about 40%.
too. Hence internal node X is not
In view of power consumption of clock
connected with Vdd or GND during
driver, the new CPSFF outperforms
most pulse windows, it is essentially
prior arts in flip-flop design by about
floating periodically. With feature size
24%. Furthermore, several low power
shrinking, dynamic
more
techniques, including low swing and
prone to noise interruption because of
double edge clocking, can be explored
the un driven dynamic node. If a
to incorporate into the new flip-flop to
nearby noise discharges the node X,
build clocking systems. Fig 7 Show the
pMOS transistor P3 will be partially
simulation
on, and a glitch will appear on output
triggered Flip Flop. Fig 8 & 9 shows the
node Q. In a Nano scale circuit, a
h- spiece & DSCH models of the
glitch not only consumes power but
designed Flip flop. DC sweep analysis of
could propagate to the next stage
the designed Flip Flop is shown in Fig.
which
10.
makes
the
node
is
system
more
result
of
double
edge
vulnerable to noise. Hence, CDMFF
could not be used in noise intensive
environment. Unlike CDMFF, other
dynamic flip-flops employ structure to
prevent
the
floating
point.
For
example, SDFF [3] has a keeper at
node X while HLFF [2], and CCFF [1]
have a transistor connecting to Vdd
when D=0, respectively. Both methods
Figure 7 Simulation Result for DET Flip Flop
serve to increase noise robustness of
node X [10].
3. Results & Conclusions
In this paper, a study is made on
the variety of design techniques for low
power clocking system is reviewed. One
effective method, reducing capacity of
the clock load by minimizing number of
clocked
Following
transistor,
the
is
approach,
ISSN: 2231-5381
elaborated.
one
Figure 8 H-spice model of the designed Flip Flop
novel
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
References:
[1] Volnei A. Pedroni, „Circuit Design
with VHDL‟, MIT Press, England.
[2] Charless H. Roth, Jr (2005) „Digital
Systems Design Using VHDL‟, 3 rd edition,
Thomson Asia private limited, Singapore.
[3] Bhaskar .J (2004) „A VHDL Primer‟,
3rd Edition.
Figure 9 DSCH2 model of the designed Flip Flop
[4] H. Kawaguchi and T. Sakurai, “A
reduced clock-swing flip-flop (RCSFF) for
63% power reduction,” IEEE J. SolidState Circuits, vol. 33, no. 5, pp. 807–
811, May 1998.
[5] P. Zhao, J. McNeely, S.Venigalla, G. P.
Kumar,M.
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Figure 10 DC Sweep Analysis
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B.
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[7] P. Zhao, T. Darwish, and M. Bayoumi,
Figure 11 Simulation Results of the Designed Flip Flop
conditional
Acknowledgements
the
“High-performance
discharge
and
lowpower
flip-flop,”
IEEE
The authors would like to thank
Trans. Very Large Scale Integr. (VLSI)
anonymous
Syst., vol. 12, no. 5, pp. 477–484, May
reviewers
for
their
comments which were very helpful in
2004.
improving the quality and presentation
[8] C. L. Kim and S. Kang, “A low-
of this paper.
swing clock double edge-triggered flipflop,” IEEE J. Solid-State Circuits, vol.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
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[10]
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Authors Profile:
Parisapogu Ravi Kumar
is Pursuing his M. Tech
from, Amrita Sai Institute Of
Science
And
Technology,
Kanchikacharla, A.P, India in
the
department
of
Electronics & Communications Engineering
(ECE) with specialization in VLSI & ES.
J.
Deenamani
is
working as an Assistant
Professor
in
the
Department of ECE in ,
Amrita Sai Institute Of
Science
And
Technology, Kanchikacharla, A.P. She has 5
years
of
Teaching
Experience
various
organizations.
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