Microprocessors
2nd stage
7-3-2013
Lec. (12)
College of sciences for women ((())) Dept. of computer sciences
Year 2012-2013
15. Evolution of CISC Processors
The evolution of CISC designs can be attributed to the desire of early designers to
efficiently use two of the most expensive resources, memory and processor, in a computer
system. In the early days of computing, memory was very expensive and small in capacity.
This forced the designers to devise high-density code: that is, each instruction should do more
work so that the total program size can be reduced. Since instructions are implemented in
hardware, this goal could not be achieved until the late 1950s due to implementation
complexity. In 1953, Wilkes and Stinger proposed microprogramming to deal with the
complexity of implementing complex instructions.
The introduction of microprogramming facilitated cost-effective implementation of
complex instructions by using microcode. Microprogramming has not only aided in
implementing complex instructions, it has also provided some additional advantages. Since
microprogrammed control units use small fast memories to hold the microcode, the impact of
memory access latency on performance could be reduced. Microprogramming also facilitates
development of low-cost members of a processor family by simply changing the microcode.
Another advantage of implementing complex instructions in microcode is that the
instructions can be tailored to high-level language constructs such as while loops.
So far, we have concentrated on the memory resource. In the early days, effective
processor utilization was also important. High code density also helps improve execution
efficiency. As an example, consider the Pentium’s string instructions, which autoincrement
the index registers. Each instruction typically requires two instructions on a RISC processor.
As another example, consider the VAX-11/780, the ultimate CISC processor. It was
introduced in 1978 and supported 22 addressing modes as opposed to 11 on the Intel 486 that
was introduced more than a decade later. The VAX instruction size can range from 2 to 57
bytes, a as shown in Table 3.
Lecturer: Salah Mahdi Saleh
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Table 3 Characteristics of some CISC and RISC processors
To illustrate how code density affects execution efficiency, consider the autoincrement
addressing mode of the VAX processor. In this addressing mode, a single instruction can read
data from memory, add contents of a register to it, write back the result to the memory, and
increment the memory pointer. Actions of this instruction are summarized below:
(R2) = (R2)+ R3; R2 = R2+1
In this example, the R2 register holds the memory pointer. To implement this CISC
instruction,
we need four RISC instructions:
R4 = (R2) ; load memory contents
R4 = R4+R3 ; add contents of R3
(R2) = R4 ; store the result
R2 = R2+1 ; increment memory address
The CISC instruction, in general, executes faster than the four RISC instructions. That,
of course, was the reason for designing complex instructions in the first place.
Lecturer: Salah Mahdi Saleh
70
16. RISC Design Principles
The best way to understand RISC is to treat it as a concept to design processors.
Although initial RISC processors had fewer instructions compared to their CISC
counterparts, the new generation of RISC processors has hundreds of instructions, some of
which are as complex as the CISC instructions. It could be argued that such systems are really
hybrids of CISC and RISC. In any case, there are certain principles that most RISC designs
follow. Note that some of these characteristics are intertwined. For example, designing an
instruction set in which each instruction takes only one clock cycle to execute demands
register-based operands, which in turn suggests that we need a large number of registers.
16.1 Simple Operations
The objective is to design simple instructions so that each can execute in one cycle. This
property simplifies processor design. Note that a cycle is defined as the time required to
fetch two operands from registers, perform an ALU operation, and store the result in a
register. The advantage of simple instructions is that there is no need for microcode and
operations can be hardwired.
16.2 Register-to-Register Operations
A typical CISC instruction set includes not only register-to-register operations, but also
register-to-memory and memory-to-memory operations. The Pentium, for instance, allows
register-to-register as well as register-to-memory operations; it does not allow memory-tomemory operations. The VAX 11/780, on the other hand, allows memory-to-memory
operations as well.
RISC processors allow only special load and store operations to access memory. The
rest of the operations work on a register-to-register basis. This feature simplifies instruction
set design as it allows execution of instructions at a one-instruction-per-cycle rate.
Restricting most instruction operands to registers also simplifies the control unit.
Lecturer: Salah Mahdi Saleh
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16.3 Simple Addressing Modes
Simple addressing modes allow fast address computation of operands. Since RISC
processors employ register-to-register instructions, most instructions use register-based
addressing. Only the load and store instructions need a memory addressing mode. RISC
processors provide very few addressing modes: often just one or two. They provide the basic
register indirect addressing mode, often allowing a small displacement that is either relative
or absolute.
16.4 Large Number of Registers
Since RISC processors use register-to-register operations, we need to have a large
number of registers. A large register set can provide ample opportunities for the compiler
to optimize their usage. Another advantage with a large register set is that we can minimize
the overhead associated with procedure calls and returns.
16.5 Fixed-Length, Simple Instruction Format
RISC processors use fixed-length instructions. Variable-length instructions can cause
implementation and execution inefficiencies. For example, we may not know if there is
another word that needs to be fetched until we decode the first word. Along with fixed-length
instruction size, RISC processors also use a simple instruction format. The boundaries of
various fields in an instruction such as opcode and source operands are fixed. This allows for
efficient decoding and scheduling of instructions. For example, both PowerPC and MIPS
processors use six bits for opcode specification.
It is worth mentioning at this point that the following set of common characteristics
among RISC machines is observed:
1. Fixed-length instructions.
2. Limited number of instructions (128 or less).
3. Limited set of simple addressing modes (minimum of two: indexed and
PC-relative).
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4. All operations are performed on registers; no memory operations.
5. Only two memory operations: Load and Store.
6. Pipelined instruction execution.
7. Large number of general-purpose registers or the use of advanced compiler
technology to optimize register usage.
8. One instruction per clock cycle.
9. Hardwired control unit design rather than microprogramming
CISC features:
1-CISC processors use variable-length instructions to accommodate various complex
addressing modes.
2-In CISC processors like the Pentium, operands can be in memory: Part of the reason for
using variable length instructions is that CISC processors tend to provide complex
addressing modes
3-A program (a software-based approach called microprogram control is used) is used to
generate the control signals.
4-CISC processors such as the Pentium provide a wide variety of addressing modes
Lecturer: Salah Mahdi Saleh
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