A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing
Extraction for Wearable Cardiovascular Monitoring
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Citation
He, David Da, and Charles G. Sodini. “A 58 nW ECG ASIC With
Motion-Tolerant Heartbeat Timing Extraction for Wearable
Cardiovascular Monitoring.” IEEE Transactions on Biomedical
Circuits and Systems 9, no. 3 (June 2015): 370–376.
As Published
http://dx.doi.org/10.1109/TBCAS.2014.2346761
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Version
Author's final manuscript
Accessed
Thu May 26 19:34:46 EDT 2016
Citable Link
http://hdl.handle.net/1721.1/102273
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Creative Commons Attribution-Noncommercial-Share Alike
Detailed Terms
http://creativecommons.org/licenses/by-nc-sa/4.0/
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
1
A 58nW ECG ASIC with Motion-tolerant Heartbeat
Timing Extraction for Wearable Cardiovascular
Monitoring
David Da He, and Charles G. Sodini, Fellow, IEEE
Abstract—An ASIC for wearable cardiovascular monitoring
is implemented using a topology that takes advantage of the
electrocardiogram’s (ECG) waveform to replace the traditional
ECG instrumentation amplifier, ADC, and signal processor with
a single chip solution. The ASIC can extract heartbeat timings
in the presence of baseline drift, muscle artifact, and signal
clipping. The circuit can operate with ECGs ranging from the
chest location to remote locations where the ECG magnitude is as
low as 30µV . Besides heartbeat detection, a midpoint estimation
method can accurately extract the ECG R-wave timing, enabling
the calculations of heart rate variability. With 58nW of power
consumption at 0.8V supply voltage and 0.76mm2 of active die
area in standard 0.18µm CMOS technology, the ECG ASIC
is sufficiently low power and compact to be suitable for long
term and wearable cardiovascular monitoring applications under
stringent battery and size constraints.
Index Terms—Electrocardiogram, heart rate, motion artifacts,
cardiovascular monitoring, wearable sensor.
I. I NTRODUCTION
ARDIOVASCULAR disease (CVD) affects 37% of the
United States population and is the leading cause of
death in the U.S. [1]. One type of CVD is cardiac arrhythmia,
which is characterized by irregular heartbeat intervals. The
most common form of cardiac arrhythmia is atrial fibrillation
(AF) [2]. AF occurs when the atrium exhibits rapid and irregular contractions. AF is often undiagnosed, but increases the
risk of stroke and heart failure by up to nine times [2]. Another
example of arrhythmia is premature ventricular contraction
(PVC). PVC’s can be the symptom of an underlying CVD
such as cardiomyopathy. Both AF and PVC can be identified
using continuous heartbeat timing monitoring [3].
The electrocardiogram (ECG) is a non-invasive surface measurement of the heart’s electrical potentials and is a primary
tool for the assessment of cardiac health. Traditionally, the
topology for an ECG heartbeat detection circuit consists of a
low noise instrumentation amplifier (IA), an anti-alias filter,
an ADC, and a digital processor [4] [5] [6]. This topology is
shown in Fig. 1(a) along with a labeled ECG in Fig. 1(c).
In this conventional topology, the IA amplifies the differential ECG signal with low noise op amps. The gain of the IA
is set so that the amplified output is not saturated. After the
anti-alias filter, the ADC uniformly quantizes the ECG signal,
treating small features such as the ECG’s P-wave and large
C
D. He and C. G. Sodini are with the Department of Electrical Engineering
and Computer Science, Massachusetts Institute of Technology, Cambridge,
MA, 02139 USA (e-mail: [email protected]; [email protected]).
Manuscript received September 16, 2014.
features such as the ECG’s R-wave with equal resolution. The
ADC is usually implemented with a medium resolution SAR
architecture to minimize power consumption. Finally, to detect
heartbeats, the digitized ECG is processed using an algorithm
to detect R-waves. Depending on the computational power
available, such an algorithm ranges from simple thresholding
to wavelet transforms. Even with a deep subthreshold digital
processor such as in [6], the digital R-wave detection algorithm
can consume three times higher power than the analog front
end.
The traditional topology is necessary for clinical ECG
measurements, where multi-lead ECG signals are acquired
with high fidelity in order to diagnose arrhythmias. These
recordings are usually quantized with at least 12 bits to
preserve P-wave details [7]. The American Heart Association
recommends a sampling frequency of at least 150Sa/s to
capture all features, while stating that a bandwidth of 1Hz to
30Hz generally produces a stable ECG without artifacts [8].
However, as mentioned, common arrhythmias can be detected with heartbeat timing monitoring where only the Rwave timing is needed. To take advantage of this fact, a
new topology is presented that removes the need for the
ADC and the signal processor to decrease the overall circuit’s
complexity, power, and area. The demonstrated ASIC receives
the ECG signal as an analog input and outputs a digital
heartbeat signal, while being tolerant to signal interferers such
as motion artifacts.
This paper is organized into the following sections. Section II explains how the proposed topology operates. Section III discusses each circuit block in detail. In Section IV,
measured results from both testbench and human subject tests
are presented. Furthermore, a method to accurately extract Rwave timings from the ASIC output is validated using clinical
data.
II. P ROPOSED C IRCUIT T OPOLOGY
The proposed topology is based on the fact that heartbeat
detection relies on the ECG’s QRS complex, which has a
higher frequency content and a greater magnitude than the
adjacent ECG features. This circuit topology is shown in
Fig. 1(b).
In Fig. 1(b), the differential ECG signal is first amplified
by a low noise programmable gain amplifier (PGA). The
PGA’s output signal is split into two paths. The first path
goes through the “QRS Amp,” which has a bandwidth that
1µ/5µ
Cin = 12pF
C
M8
BIAS
PGA
1µ/5µ+
out
Ctank
VDD
VDD
in
ECG
AV
Rp
IEEE TRANSACTIONS ON BIOMEDICALC
CIRCUITS
AND
SYSTEMS
Bank:
f
Electrodes
VPGA
+
CVDD
20fF ~ 1.28pF
Reset
Cin
preserves the QRS complex. The second path
goes through
Rp
CV
f Bank:
CM
the “Baseline Amp,” which
an equal gain but a lower
20fF ~has
1.28pF
Reset
Gnd Vbaseline
CM
bandwidth to preserve only the low frequency
drift
caused by motion artifacts.
VCM Then, a positive inline DC offset
VCMadaptive threshold
Gnd an
VDC is added to VBaseline to create
VBaseline+DC . A QRS complex (or heartbeat) occurs whenever VQRS > VBaseline+DC . This comparison is performed by
a comparator, which consequently pulses a high DOU T when
a heartbeat is detected.
ECG
Electrodes
ECG
Electrodes
Processor
for Heartbeat
Processor Detection
ADC
IA
Anti-alias
IA
ADC
(a)
ECG
ECG
PGA
Electrodes PGA
Electrodes
VQRS
QRS
VQRS
Amp
VDC
V
V
+
+
VDC
V
+
Amp
DOUT
DOUT
V
Baseline Baseline
Baseline+DC Baseline+DC
BaselineBaseline
Amp
+
Ground
Ground
Electrode
Electrode
(Optional)
(Optional)
Circuit gnd
QRS
Amp
-
CGnd
2
Vout M5
VDD
M4
M6
rate range or when DOU T becomes irregularly spaced. Once
M5 routine can be rerun to update
detected,Cthe +-initial
calibration
V
M4
M6
M3
Gnd
VCDC
. If the irregularCD
OU T is caused by actual irregular RVDD
Gnd
waves, then the recalibration will be unable to complete, in
which case Gnd
arrhythmiaGnd
can be implied.
There are several advantages
to thisVBaseline+DC
topology in terms
Φb
1
of circuit design. First, no signal
processor
or ADC is reC
2.9pF
Φ reduces
Φ significantly
quired,
which
the
device’s
power and
VDD
Φb
Φb
C
+
V
area. Second,
a low
voltage supply is possible because a
2.9pF
clipped R-wave that exceeds the amplifier’s output range still
Digital
Outputs
Φb
Φ
C
Bank: heartbeat
C
Bank: Third, any comparator offset
possesses
information.
15fF ~ 155fF
40fF ~ 5.1pF
is automatically compensated due to the VDC calibration.
Fourth, amplifier
linearity is unimportant because the signal
VBaseline
Gnd
path is highly nonlinear. In terms of practical usage, this
topology is tolerant
to
40fF motion artifacts because the signal is
QRS
differentially Amp
compared against its own baseline. Furthermore,
no predefined 960fF
subject-dependent parameters are needed.
M3
Gnd
VBaseline
Gnd
VDC
CC = 1.9pF
DC
tank
VDC
DC
Gnd
1µ/5µ 1µ/5µ
VDD
-
-
Gnd
VQRS
AV
+
VDD
M7
VBIAS
M8
III. C IRCUIT D ESIGN
Microcontroller:
Microcontroller:
VDC calibration
Circuit gnd
CC = 560fF
A. Programmable Gain Amplifier
VDC calibration
VPGA
Vin_n
M1
Vin_p
M2
Baseline
40fF
PGA’sAmp
function is
Vout
VDD
CC
The
to amplify the ECG directly from the
M5
M4
M6
electrodes with960fFminimal circuit noise and M3power while
having
a range of gain
to
adapt
to
various
ECG
amplitudes.
Fig.
2
Gnd
Gnd
A
VBaseline
shows the schematic +of the PGA, which consists of an op amp
15pF
in the differenceC =configuration.
(b)
1µ/5µ 1µ/5µ
0.8
Amp Outputs [V]
Vin_p
VDD
Digital Outputs
for Heartbeat
Detection
Anti-alias
CC = 1.9pF
+
CVDC
M1 - VDC M2
Vin_n
R
0.6
V
VQRS
QRS
V
V
VBaseline
Baseline
QRS
Complex
C
V
VBaseline+DC
Baseline+DC
0.4
Cf Bank: 20fF ~ 1.28pF
VCM
0.2
VDC
1µ/5µ
VBIAS
1µ/5µ
VDD
M7
M8
-
ECG
Electrodes
1
VDD
Rp > 10TΩ
Cin = 12pF
Q S
0
DOUT [Digital]
T
P
Reset
AV
+
Vin_n
M1
VPGA
Vin_p
M2
Vout
VDD
Cin
CC = 1.9pF
Rp
Cf Bank:
M5
20fF ~ 1.28pF
Reset
M3
M4
M6
VCM
0
0
Gnd VCM
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Gnd
2
Time [s]
Fig. 2. The PGA schematic.
(c)
Fig. 1. a) The traditional topology for ECG heartbeat detection, b) the
proposed topology with voltage nodes labeled, and c) an ECG waveform
illustrating the QRS complex, baseline, baseline with VDC offset, and digital
output.
IA
Processor
for Heartbeat
Detection
ECG
Electrodes
PGA
ADC
Anti-alias
Ground
Electrode
(Optional)
QRS
Amp
Baseline
Amp
Circuit gnd
Digital Outputs
VQRS
VBaseline
VDC
-
+
To correctly set VDC , it is incremented until the period
between DOU T pulses is regular and is in the range of human
beat-to-beat interval. As shown in Fig. 1(c), there is a wide
range of valid VDC values since VDC can be set at any
level between the R-wave and the next highest amplitude
feature (usually the T-wave). Because respiration causes slight
baseline modulation of the ECG, we use four respiratory
cycles to complete the VDC calibration routine, which takes
20 seconds on average. This calibration is performed at the
beginning of measurement by an external microcontroller that
consumes 5µA at a clock frequency of 4kHz, which is
powered off afterwards.
During measurement, VDC may need to be recalibrated if
the measurement condition changes significantly due to motion
artifacts or muscle noise. The need to recalibrate VDC can be
detected in real time when DOU T exceeds the human heart
1.8mm
Sensing a biopotential such as the ECG creates several
circuit requirements. First, because the ECG amplitudes vary
between different body locations and different subjects by up
+
to two orders of magnitude, an adjustable gain is required.
The gain of the PGA is set by Cin /Cf , where Cin = 12pF
and Cf is implemented as a 6-bit binary weighted capacitor
bank of 20f F to 1.28pF to adjust the PGA gain from 19dB
to 56dB.
Second, the AgCl electrode’s half-cell potential generates
approximately 200mV of near-DC electrode offset voltage
(EOV) which would saturate the amplifier if not removed. To
filter this EOV, PMOS pseudo-resistors (Rp ) are used [9]. The
Rp ’s are greater than 10T Ω but only occupy 10µm2 , thus enabling on-die sub-Hz high pass filters and effectively removing
the EOV. The large Rp also allows the DC biasing of the amplifier inputs while maintaining a high input impedance, which
is needed due to the capacitive Cin . Furthermore, because the
input impedance is significantly larger than Relec ≈ 300kΩ,
any differential voltage caused by unequal and varying Relec
(such as during motion) is negligible.
ECG
Electrodes
DOUT
VBaseline+DC
Microcontroller:
VDC calibration
Voltage
Reference
m
PGA,
QRS Amp,
and Baseline Amp
Current
Reference
VDC
Comparator
M3
+
ΦCVDC
-
CVDD
VBaseline+DC
Vout_p
M4
VDC
VL
VR
M1
M2
SR Latch
CGnd V
QRS
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
3
Gnd
Φ
Gnd
It should be noted that the high impedance at the PGA
input nodes leads to long start-up settling times. As a solution,
reset switches shown in Fig. 2 are added to the PGA inputs to
immediately shunt the input nodes to their final common-mode
DC voltage VCM during start-up.
The PGA’s op amp is a two-stage Miller-compensated op
amp. This topology is chosen because of its compatibility
with low voltage supply, wide output swing, and self-biasing.
Due to the low frequency and bandwidth requirements of
ECG signals (1Hz − 25Hz), the PGA can operate in deep
subthreshold with 90nA of bias current. The low gm leads to
a greater thermal noise spectral density, but the thermal noise
contribution is limited because of the PGA’s low bandwidth.
At this frequency, the dominant noise source is 1/f noise.
Chopper modulation at the PGA inputs is a possible method to
eliminate 1/f noise. However, chopper switches introduce a
current path between the PGA inputs. If there is any input
offset voltage, then an offset current would exist that can
saturate the PGA through the high resistance feedback Rp .
A solution is to use a GM − C servo-loop to provide a
current path, but it consumes additional current [10]. Without
chopping, the input 1/f noise can be designed to be within
1µVrms (0.5Hz − 50Hz) by appropriate transistor sizing,
which is acceptable for ECG signals that are typically at 1mV .
For these reasons, chopper modulation is not used.
The input-referred 1/f noise spectral density for this op
amp is shown in Equation (1), where (gm3 /gm1 )2 = 1 when
in subthreshold [11]:
2
2
vif
2 · K1
gm3
2 · K3
sub
=
+
(1)
·
2
2 f
∆f
W1 L1 Cox f
gm1
W3 L3 Cox
tank
VDC
DC
VDD
Gnd
QRS
Amp
Gnd
40fF
1µ/5µ 1µ/5µ
VTop
960fF
-
VTop
Gnd
VPGA
VDD
Flipb
Baseline
+
V
- DC Amp
40fF
Vin_n
M1
VBaseline
Gnd
M16
M15
VTop
VBot
M6
VDD
+
CC = 15pF
M13
VL
M14
M11
Vout_p
C Bank:
~ 1.28pF
Fig. 3. The QRS
Amp and
the20fFBaseline
Amp schematic.
V
M9 M5
f
CM
1
Rp > 10TΩ
VR
M12
M8
M7
Vout_n
Reset
Flipb
M4
M3
AV
Vout
CC
M5
Flipb
Gnd
Vin_p
M2
DD
1µ/5µ 1µ/5µ
960fF
VBot
M8
ΦVb
Reversed
+
- VDC
CVDC
VDD
M7
VBIAS
CC = 560fF
CVDC
VBot
VQRS
AV
+
VBaseline+DC
V
Vout_n
M6 M10
VDD
DD
Gnd
M7
V
M8
Both
and Baseline
of
CtankAmps have a Vfixed gain
VDDC QRS
= 12pF
ECGF/40f F = 28dB,A thus resulting
960f
in
an
overall
gain
V
V
M1
M2
Φ
V
Electrodes
V
range of 47dB
to+ 84dB.+ At this overall gainV range
and with
V
C
C
V
V
V
VDC
DC
R
Bank:
VCDD
= 0.8V , Cthe
can be usedM5to measure
- full dynamic
CGndrange M3
VDD
V
Reset
ECG signalsV at various wearable locations
onΦ M4
the body M6
where
Gnd
V
Gnd
Gnd3mV
the ECG
ranges
from
approximately
30µV
to
.
pp
pp
VBaseline
Gnd
Gnd
1µ/5µ
BIAS
1µ/5µ
DD
in
in_n
V
M3
in_p
L
DD
R
PGA
in
M2
M1
Baseline+DC
p
f
M4
Vout_p
out
SR Latch
CC = 1.9pF
QRS
20fF ~ 1.28pF
DD
M16
M15
CM
M13
VL
M11
CM
M14
M8
M7
Vout_n
VR
M12
Vout_p
Vout_n
DOUT
+
C. VDC Generator
CVDC
VDC
M9
M6 M10
M5
-
Gnd
Processor
for Heartbeat
Detection
Φb
Φb
Φb
Ileak
ADC
IA
Anti-aliasDD
Φ
VBaseline+DC
.
Gnd
M4
VQRS
QRS
M1
Amp
Ground
Electrode
(Optional)
Vout_p
The VDC
M2
Baseline
Amp
Φ
VBaseline
Gnd
QRS
VDC
-
DOUT
VBaseline+DC
Gnd
Circuit gnd
-
Φb
Microcontroller:
VDC calibration
Φb
Φb
VDD
VA
Φb
VM
Φ VA
Ileak
Φb
1
R
L
ECG
PGA
Baseline+DC
Electrodes
Φ
Digital Outputs
to produce
an adaptive threshold
Φ
V
V
SR Latch
generator
schematic
V + is shown in Fig. 4.
V
M3
VB
CVDC
2.9pF
Φ
Gnd
Φ
Φ+
-
Ileak V
B
VDC
Φ
Φb
VBaseline+DC
V
V
1
VTop
Ctank
VDD 2.9pF
Bot
CVDC
+
- VDC
Flipb
+
V
- InDC
CVDC
Out
Top
Φb
CVDD Bank:
15fF ~ 155fF
Φ
VTop
VTop
Flipb
VBot
CGnd Bank:
40fF ~ 5.1pF
VBot
VTop
VBot
Flipb
VBaseline
C
CVDC
VDC
+
- VDC
1
Φb
Gnd
Reversed
Flipb
VDD
QRS
VTop VBot
Amp
960fF
Ctank
Gnd
VDD
CVDD
Gnd
CVDC
VPGA
CVDC
Gnd
VBaseline+DC
1µ/5µ
1µ/5µ
+
- VDC
CVDC
CVDD
VBaseline
CGnd
Gnd
VDD
+
V
- DC
VQRSCVDC
AV
+
+
- VDC
VBaseline
1
40fF
M7
VBIAS
CVDD
CGnd
CC = 560fF
CGnd
Vin_n
M1
Gnd
Gnd
Baseline
(a)
+
V
Amp
-
40fF
(b)
Φb
CVDD
CGnd in a) clock phase Φb and b) clock phase Φ.
Fig.
5. The VDC generator
M3
1µ/5µ 1µ/5µ
VDD
960fF
Φb
Gnd
Φb +
VBaseline
AV
+
V
- DC
Φ
VDD
CM5
tank
M4 2.9pF
Φb
Gnd
VBaseline+DC
1
Ctank
Φ
CVDC
2.9pF
Vin_p
M2
DC
Gnd
VBaseline+DC
Ctank
Flipb
Fig. 4. The VDC generator schematic.
B. QRS and Baseline Amplifiers
Revers
1
Gnd
+
V
- DC
Ileak
VM
VA
VA
VB
Φ
The VDCV generator’s function
CVDD
CGnd is to add VDC to VBaseline
ECG
Electrodes
VBot
The PGA’s output is connected to the inputs of the QRS
and Baseline Amps. The function of the QRS Amp is to
amplify the ECG signal with a bandwidth that passes the QRS
complex. Meanwhile, the Baseline Amp has the same gain but
has a lower bandwidth that only passes the baseline signal.
In Fig. 3, both amplifiers use identical two-stage Millercompensated op amps in the non-inverting configuration. The
only difference is in the compensation capacitors (CC ). The
1
Gnd
Baseline
+
According to Equation (1), several design choices are made
to minimize 1/f noise. First, PMOS input transistors are
used because they offer lower noise coefficients than NMOS
transistors: K1 = Kp < Kn . Second, increasing W1 and
L1 will reduce the noise contribution of the input transistors.
However, excessive input transistor area will introduce significant parasitic capacitance at the drain of M2. This decreases
the frequency of the second pole and lowers the phase margin.
A dimension of 864µm/1.5µm (96 fingers of 9µm/1.5µm) is
chosen so that M1 and M2’s 1/f noise contributes to 40% of
total input noise. Third, increasing W3 and L3 will reduce the
noise contribution of the mirror transistors. However, signal
swing places an upper limit on W3 and process technology
places an upper limit on L3 . A dimension of 100µm/20µm
(8 fingers of 12.5µm/20µm) is chosen so that M3 and M4’s
1/f noise contributes to 20% of total input noise.
VBaseline+DC
Φ
Miller multiplied CC and ba 0.5nA 1bias current create very
C
low
while
being
2.9pF area-efficient. For the QRS
Φ
Φ
VDD corner frequencies
Φ
Φb
b
C 560f
+ F sets the
Φ
Amp, CC =2.9pF
low
passΦbcorner frequency at
b
V
Ileak V
VM For the
B
25Hz, Φwhich
passes theVQRS
complex.
Baseline
Amp,
b
A
Ileak
VDD
Φ
Φ
b
CVCC =Bank:
15pF sets
the
low
pass
corner
frequency
at
1Hz,
which
C
Bank:
VB
A ~ 155fF
15fF
40fF ~ 5.1pF
Φ
Φ
only
passes the baseline drift.
Pseudo-resistors
are usedOut
to biasIn
Φ
the inverting
node.
V Gnd
CVDD Bank:
Φb
Φ
CGnd Bank:
C
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
4
CV DD is a 4-bit binary weighted capacitor bank of 15f F to
155f F , and CGnd is a 7-bit binary weighted capacitor bank of
40f F to 5.1pF . CV DD and CGnd values are selected during
the initial VDC calibration by the microcontroller.
Non-overlapping clock phases Φ and Φb are generated onchip at 2.0kHz by a clock generator. The clock frequency
is chosen as a compromise between low power (favors lower
frequency) and low charge leakage (favors higher frequency).
During clock phase
Φb (Fig. 5(a)), CV DD and CGnd are
V
respectively reset
M15 M16 to VDD and ground. During the following
clock phase
Φ (Fig. 5(b)),
CV DC is charged to a final voltage
M13
M14
V
V
M11
M12
of VDC =
VM7DD CV M8DD
/(CV DD +CGnd ). During the following
V
V
clock phase
Φb , VVDC is added
to VBaseline
to produce
D
M6 M10
M9 M5
VBaseline+DC , while CV DD and CGnd are again reset. Ctank
Gnd
is present to reduce
voltage ripples. With the selectable ranges
V
of CV DD and CGnd , VDC can be adjusted from 0% to 80% of
V
M3
M4
Φ
VDD . This
range
covers
most situations where the interferer
V
V
SR Latch
or noise
occupies
to 80% of VDD while having a lower
M2 up V
M1
V
amplitude than
the R-wave.
Φ
In consideration
Gnd for long term at-home usage where the
ECG electrodes are applied by the wearer, the VDC generator
has the ability to generate negative
VΦDC
if the user accidentally
Φb
b
Ileak V
V
Bby the two digital
M
reversesΦthe
electrodes.
This
is
symbolized
b
VA
Ileak
VDD
blocks
in
Fig.
4
that
can
flip
C
during
phase Φb . In the
V
VA
VB
Φ V DC
Φ
In then the
Out
case thatΦ the ECG
is reversed and CV DC is flipped,
M15 M16
Gnd
heartbeat M13
occurs
whenM14DOU T = 01 instead of DOU T = 1.
V
TheseV digital
blocksM8are
M11
M12 expanded in Fig. 6(a).Gnd
M7
DD
R
L
out_n
out_p
out_n
OUT
DD
out_p
L
R
QRS
Baseline+DC
Ileak by reducing the |VDS | of the switch closest to the
capacitor. All switch and buffer transistors are minimally sized
(PMOS: 400nm/180nm, NMOS: 220nm/180nm) to reduce
the effect of charge injection.
D. Comparator
The comparator’s role is to output a digital pulse when
a QRS complex has occurred, which is when VQRS >
VBaseline+DC . A dynamic latched comparator based on [13]
is used (Fig. 7). The dynamic topology is chosen because it
consumes power only when latching. This topology offers the
additional benefit of only using a single clock signal Φ, thus
placing no requirements on Φb timing.
M11 and M12 are added to reduce short circuit currents
through M13-M16 when VL and VR are transitioning. This is
important because short circuit currents of several nano-amps
can be a significant portion of the overall power. VBaseline+DC
contains switching transients from the VDC generator. However, these transients are designed to occur with Φb , which do
not affect comparator accuracy because comparator latching
occurs with Φ.
VDD
DD
M15
M13
VL
R
L
Vout_n
M9
Vout_p
VBot
CVDC
+
- VDC
VTop
M11
M14
M8
M7
Vout_n
Vout_n
VTop
M6 M10
M5
M16
M12
VR
Vout_p
Vout_n
DOUT
M9
DOUT
M6 M10
M5
Gnd
Flipb
VDD
+
V
- ΦDC
CVDC
VBaseline+DC
M3
M4
VL
VR
M1
M2
Gnd
Φb
Vout_p
Reversed
SR Latch
Flipb
VQRS
VDD
Flipb
Φ
VBot
Φ
VTop
VBaseline+DC
VBot
M3
Vout_p
M4
VL
VR
M1
M2
SR Latch
VQRS
Gnd
Φ
(a) VBaseline+DC
VDD
Φb
Ctank
VA
Ileak
+
CVDC VB- VDC
VA
CVDD
CGnd
Φ
Gnd
Gnd
VBaseline
1
Φb
Φb
VM
Gnd
Ileak V
B
Fig. 7. The dynamic latched comparator with SR latch. The comparator is
based on [13].
VDD
Φ
Φ
Out
Φb
In
1
Gnd
Gnd
CVDC
+
V
- DC
(b)
VBot
Fig. 6. V
The
Top VDC generator’s internal circuit blocks: a) CV DC can be flipped
during phase Φb in the case of reversed electrodes, and b) the low leakage
Gnd
Flipb capacitor discharge [12].
switch implementation to prevent
Φb
+
VBaseline+DC
+Φ
Flipb
CVDC
V
CVDC - VbDC
1
- DCthe switching
Because
frequency isReversed
only
2.0kHz and
VGnd
Top
C
CVDD
Ctank
2.9pF
Φ
Φ , a leakage current
CV DC
of only 5.8pA can reduce
VDD = 2.9pF
Φb Flipb
Φb
C
+
VDC by
1mV
between
V clock cycles. To reduce switch leakage,
2.9pF VBot
stacked switches with aVTop
push-pull
buffer are implemented
VBot
Φ
Φ
based
on
[12].
The
switch
schematic
is
shown in Fig. 6(b) and
b
C
Bank:
C
Bank:
15fF ~ 155fF
40fF4.
~ 5.1pF
is used
for all switches in Fig.
The
two stacked switches
VBaseline+DC
in Fig. 6(b) exponentially reduce1 the subthreshold Ileak by
VBaseline
Gnd
Ctank
VDD the
decreasing
|VGS | of the
two switches. The push-pull buffer
drives VM to the same voltage as VB , thus further decreasing
VDC
DC
VDD
CVDD
Gnd
QRS
+
CVDC Amp
- VDC
Out
producesΦan input-referred comparator offset range of −13mV
Gnd
to 16mV . However, as mentioned in Section1II, no comparator
offset compensation is needed due to the VDC calibration
Gnd
routine. The final output of the SR latch, DOU T , is a digital
signal that pulses when a heartbeat is detected.
VTop VBot
VTop
E. Peripheral Circuits
Flipb
All peripheral circuits
and passive components are impleΦb current
+on-chip. These circuits include
mented
a fast startup
+
CVDC
V
CVDC - VDC
Reversed
- DC
reference for the amplifiers based on [14], a diode ladder
voltage reference to generate the common-mode
voltage for
Flipb
the PGA, and a clock generator that provides the 2.0kHz
VBot
non-overlapping
clock signals for the VDC generator and the
VTop VBot
comparator.
CGnd
1µ/5µ 1µ/5µ
VBaseline
Gnd
VM
40fF
960fF
Gnd
Φb
Ileak V
B
V
A
I
M1-M4 gate
lengths are set at 1µm to reduce geometry
VDD
leak
VA
VB
mismatch.
A Monte
Carlo mismatch
of 100 runs
Φ simulation
Φ
Φb
Gnd
A
V
VDD
V
VDD
1
VBaseline+DC
In
Flipb
5
IV. M EASUREMENT R ESULTS
The ASIC is fabricated using a standard TSMC 0.18µm
1P6M CMOS technology. The die area is 1.8mm × 1.8mm
with an active area of 0.76mm2 as shown in Fig. 8.
R
Amp Outputs [V]
0.6
Total Gain
90
V
VQRS
QRS
V
VBaseline
Baseline
QRS
Complex
80
V
VBaseline+DC
Baseline+DC
Bandwidth
0.4
0.2
70
Q S
0
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Total Gain [dB]
DOUT [Digital]
VDC
T
P
2
Time [s]
1.8mm
50
40
Voltage
Reference
PGA,
QRS Amp,
and Baseline Amp
-6
10
60
Input-referred
Noise
30
Current
Reference
Input-referred Noise [V/(Hz)1/2]
0.8
100
1.8mm
20
Comparator
Clock
Gen.
VDC
Gen.
10
-7
0
10
Config. Registers
1
10
Frequency [Hz]
2
10
10
3
10
Test Blocks
Fig. 9. The measured PGA-QRS Amp signal path’s gain response and noise
response. 0.8
Total Gain
-7
10
0
1
10
10
3
10
2
10
Frequency [Hz]
10
VBaseline+DC
VQRS
0.8
0.8
0.7
Amp Outputs [V]
Amp Outputs [V]
0.7
0.6
0.6
A. Testbench Measurements
The ECG’s amplification path goes through the PGA and
then the QRS Amp. Fig. 9 shows the gain response and inputreferred noise response at the highest gain setting. In the gain
response, the plot shows the sub-Hz high pass corner enabled
by the PGA and QRS Amp’s pseudo-resistors, the low pass
corner implemented by the QRS Amp’s low gm and large
Cc , and the 40dB/dec falloff at higher frequencies due to the
two poles from the PGA and the QRS Amp. In terms of noise
response,
1/f characteristic below 10Hz
√ the circuit exhibits a √
(or 1/ f when plotted as V / Hz).
0.5
0.4
0.3
0.5
0.4
0.3
0.2
0.2
0.1
0.1
[V]
0
0.8
OUT
0.8
D
DOUT [V]
0
0
0.80
2
4
6
8
0
0.80
10
Time [s]
8
10
2
22
4
6
4 4 Time [s] 6 6
Time[s][s]
Time
8
88
0.8
0
0
Amp Outputs [V]
[V]
Amp Outputs [V]
OUT
D
6
66
8
88
10
1010
VBaseline+DC
VQRS
4
6
8
10
6
8
10
6
8
10
0.4
0.4
0.8
0.3
0.2
0
0.10
DOUT [V]
2
Time [s]
Time[s][s]
Time
2
4
Time [s]
0.8
0.8
0
0
0.7
10
Amp Outputs [V]
Time [s]
2
4
Time [s]
0.6
0.5
0.4
0.3
0.2
0.1
0
2
4
0.80
0.8
0
0.8
2
4
6
8
10
6
8
10
0
0.8
000
00
0.7
2
22
4
6
4 4 Time [s] 6 6
Time[s][s]
Time
Time [s]
0.8
0
0
2
Time [s]
4
6
8
10
Time [s]
VBaseline+DC
VQRS
8
88
10
1010
0.6
0.5
0.4
TABLE I
S IMULATED VS . MEASURED RESULTS FROM THE PGA-QRS A MP SIGNAL
PATH .
0.3
0.2
0.1
0
2
4
6
8
0.8
0
0
10
2
4
Time [s]
6
8
10
Time [s]
Parameter
Programmable gain
range
Passband
Unity-gain bandwidth
Input-referred noise
(in band)
CMRR
PSRR
Current consumption
(at 0.8 V)
Simulated
47 dB – 84 dB
Measured
47 dB – 88 dB
0.52 Hz – 51 Hz
6.4 kHz
0.99 µV rms
0.50 Hz – 22 Hz
2.9 kHz
2.7 µV rms
3mm x 3mm
QFN-16 ECG ASIC
ECG Electrode 2
ECG Electrode 1
1
VQRS
VBaseline+DC
VQRS
0.6
0.4
0.2
0
0.5
0
10
15
20
25
30
5
10
15
20
25
30
5
10
15
20
25
30
35
40
45
0.4
0.3
40
45
0.1
19
19.1
19.2
19
19.1
19.2
19
19.1
19.2
1
35
0.5
0.5
0
Midpoint
Timing
1
1
Manual
Estimated
0
Time [s]
0.6
0.5
0.2
5
1
0.5
VBaseline+DC
0.7
0.8
Amp Outputs [V]
0
0.6
0.8
0
0.5
0
0.7
0.4
4
44
DOUT [V]
0.1
2
22
DOUT [V]
0.3
10
8
0.3
0.8
0.2
0.7
0.1
0.6
0
0.5
0
0
000
0.8
0.80 0
0.7
10
1010
0.5
0.4
8
6
Time [s]
0.5
DOUT [V]
6
Time [s]
0.6
0.2
DOUT [V]
4
6
Time [s]
0.6
0.3
0.8
0.8
0.8
0.5
0.2
0.7
0.7
0.7
0.4
0.1
0.6
0.6
0.6
0.3
0.50
0.5
0.5
0.2
0.4
0.4
0.8
0.4
0.1
0.3
0.3
0.3
0
0.2
0.2
0.2
0
0.10
0.8
0.1
0.1
0
00
Amp Outputs [V]
Amp Outputs [V]
0
0.8
000
00
0.7
2
4
R-waves
[V]
DAmp
[V][V]
Outputs
Outputs
Amp
OUT
Outputs [V]
Amp
[V][V]
DOUT
DOUT
[V]
DOUT
0.8
0.8
0.8
10
1010
2
[V]
D
OUT
Amp Outputs [V]
DOUT [V]
[V][V]
Outputs
Amp
Outputs
Amp
Amp
[V] Outputs [V]
Amp Outputs
0.5
0.4
8
88
4
0.6
0
[V][V] D
DOUT
DOUT
[V]
[V]
DOUT
OUT
0.6
0.3
0.8
0.8
0.8
0.2
0.7
0.7
0.7
0.1
0.6
0.6
0.6
0.50
0.5
0.5
0.4
0.4
0.4
0.8
0.3
0.3
0.3
0.2
0.2
0.2
0
0.10
0.1
0.1
0
00
4
6
4 4 Time [s] 6 6
Time[s][s]
Time
DOUT [V]
Amp Outputs [V]
0.7
2
22
VBaseline+DC
VQRS
0.6
0.6
0.3
0.8
0.5
0.5
0.5
0.2
0.7
0.4
0.4
0.4
0.1
0.6
0.3
0.3
0.3
0
0.5
0.2
0.2
0.2
0.4
0.1
0.8
0.1
0.1
0.30
00
0.2
0.800
0.1
0.8
0.8
Amp Outputs [V]
0
000
0.8
00
2
0.7
0.6
0.8
0.8
0.8
0.5
0.7
0.7
0.7
0.4
0.6
R-waves
[V][V]
Outputs
Amp
Outputs
Amp
Amp Outputs [V]
[V][V]
DOUT
DOUT
[V]
DOUT
0.8
0.8
0.8
D D [V][V]
[V][V]
Outputs
Amp
OUT
Outputs
Amp
[V] D
DOUT
Outputs [V]
Amp
[V]Outputs
OUT
Amp
[V]Outputs [V]
Amp
OUT
0.7
0.8
0.8
0.8
0.7
0.7
0.7
0.6
0.6
0.6
0.5
0.5
0.5
0.4
0.4
0.4
0.3
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
00
35
40
45
0
Time [s]
78 dB
53 dB
92 nA
0.7
Table II lists the power consumption of each circuit block
at VDD =
0.60.8V . 87% of the total power is allocated to
the PGA due to bandwidth and thermal noise considerations.
0.5 circuits consume 8.6% of the total power. The
The peripheral
ECG ASIC’s
0.4 elimination of the ADC and the signal processor
enables it to reduce power consumption. Another portion of
the power0.3
saving is contributed by the PGA’s low bandwidth.
A further source of power saving is the ECG ASIC’s low VDD ,
0.2
which is enabled by its tolerance to signal clipping.
0.1
66 dB
61 dB
64 nA
Table I compares the simulated and measured results from
the PGA-QRS Amp signal path. Increasing the transistor bias
currents did not appreciably decrease the input-referred noise,
which indicates that the in-band noise is 1/f dominated as
Fig. 9 indicates. Because of this, the actual PGA’s bias current
is lowered compared to simulation, and the reduced low pass
frequency of 22Hz remains sufficient to preserve the ECG’s
QRS complex. The measured input-referred noise is greater
than the simulated noise by 2.7 times, which is likely attributed
to differences between the transistor model’s and the actual
transistor’s 1/f characteristics. The measured level of noise is
compatible with sensing the ECG, where the QRS amplitude
is typically
1mVpp . 6
4
8
10
4 4 Time [s] 6 6
88
1010
Time[s][s]
Time
TABLE II
S IMULATED0VS . MEASURED POWER CONSUMPTION OF EACH CIRCUIT
BLOCK AT VDD = 0.8V .
DOUT [V]
Input-referred
Noise
30
20
Circuit0.8
block
PGA
QRS Amp
Baseline 0Amp
0.80
VDC generator
Comparator
Current0.7
reference
Voltage reference
0.6
Clock 0.8
generator
Total 0.8
0.8
D D [V][V]
[V][V]
Outputs
Amp
OUT
Outputs
Amp
[V] D
DOUT
Outputs [V]
Amp
[V]Outputs
OUT
Amp
[V]Outputs [V]
Amp
OUT
Total Gain [dB]
-6
10
50
40
Simulated
Power (nW)
72.8
0.5
0.5
1.62
0.3
2.2
2.2
2.0
82.0
Measured
Power (nW)
50.4
0.7
0.7
4
0.8
0.4 Time [s]
1.8
1.0
2.2
58.0
6
0.5
0.7
0.7
0.7
0.4
0.6
B. ECG Measurements
0.6
0.6
0.3
0.8
0.5
Fig. 10(a)
to 10(d) show measured ECG and digital outputs
0.5
0.5
0.2
from various
0.7
0.4 wearable ECG scenarios to demonstrate the
0.4
0.4
ASIC’s robustness
in the presence of baseline drift, muscle
0.1
0.6
0.3 attenuated signal.
artifacts, and
0.3
0.3
0
In Fig. 10(a),
0.5
0.2 the at-rest chest ECG offers 1.8mVpp of stable
signal. Here,
0.2VDC is set to 0.3V so that VBaseline+DC is
0.2
approximately
0.4
0.1 half of the VQRS amplitude. However, any VDC
0.8
0.1 0.1V and 0.65V would produce the correct
0.1
setting between
0.3
digital QRS 0output
at DOU T .
00
In Fig. 0.2
10(b), the chest ECG contains significant baseline
0
drift due to
motion.
Despite the baseline drift, the same VDC
0.8
0
2
4
6
0.8
0.8
setting as0.1
in
Fig. 10(a) results in a correct DOUTime
fact,
T . In[s]
any VDC setting between 0.1V − 0.5V would be valid. This
0
demonstrates the ASIC’s tolerance to motion artifacts because
its adaptive 0threshold
VBaseline+DC
tracks the
2
4 baseline drift.6
000
0.8
0
2
4
0
2
4
66
0.8
Time [s]
0.7
Time[s][s]
Time
[V]
Bandwidth
60
OUT
80
70
Input-referred Noise [V/(Hz)1/2]
90
VQRS
Amp Outputs [V]
100
Fig. 8. Die micrograph of the ECG ASIC with the circuit blocks labeled.
]
2
22
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
VQRS
0.2
4
0.1
6
4
Time
[s] [s]
Time
6
4
444
6
666
10 10
8
8
888
10
10
10
10
Time [s]
Time[s]
[s]
Time
Time
[s]
0 444 4Time [s]
2
22 2
2 2
8
6
66 6
4 Time
4Time
[s][s] [s]6 6
Time
TimeTime
[s] [s]
2
22
4
6
4 4 Time [s] 6 6
Time[s][s]
Time
0.8 (c)
VBaseline+DC
10
VQRS 8
88 8
8 8
VBaseline+DC
VQRS
8
88
10
1010
8
10
4
2
2
222
6
4
Time
[s] [s]
Time
8
6
4
6
444 Time [s] 666
Time[s]
[s]
Time
Time
[s]
10 10
8
4
2
8
888
6
4
8
6
4
0.6
6
2
22 2
2 2
0.5 0.5
0.4 0.4
8
88 8
8 8
0.8 0.8
2
4ECG4 Electrode62 6
TimeTime
[s] [s]
2
15
20
25
30
40
20
25
30
35
15
20
25
30
R-waves
1
35
40
VQRS
VBaseline+DC
VQRS
8
10
DOUT [V]
VQRS
VBaseline+DC
0.4
O
Amp
Outp
Amp
0.5
0.5
VBaseline+DC
0.7
0.6
0.5
0.4
0.3
0.2
5
10
15
20
25
30
35
40
0.1
45
19
19.1
19.2
1
0.5
0.5
Midpoint
Timing
VBaseline+DC
19
19.1
19.2
Midpoint
Timing
19.2
20
25
30
35
40
0
45
19.1
19.2
19
19.1
19.2
19
19.1
19.2
1
Estimated
0
10
15
20
25
Time [s]
30
35
40
45
0
Time [s]
0.5
0
VQRS
0.4
15
Manual
5
19.1
Fig. 12.
DOU T .
VBaseline+DC
0.7
0.6
10
Time [s]
VBaseline+DC
0.8
5
1
19
0.2
VBaseline+DC
6
0.6
0
0.5
45
Amp Outputs [V]
10
Amp Outputs [V]
ECG Electrode 1
10 10
8
0.3
ECG Electrode 2
VQRS
8
4
0.8
10
ECG Electrode 1
4ECG Electrode62
Time [s]
2
1
0.4
3mm x 3mm0 19
40
45
QFN-16 ECG ASIC
1
Estimated
Manual
Time [s]
2
0.8
0.5
1
0
0
0.3
0.6
0.1
45
0
10
10
10
0.7
DOUT [V]
15
0.5
3mm x 3mm
QFN-16 ECG ASIC
0.8
8
8
0.4
0
1
5
DOUT [V]
35
1
0
10
8
VBaseline+DC
1
10
6
6
0.2
0.2
5
4
4 Time [s]
Time [s]
0.5
3mm x 3mm
QFN-16 ECG ASIC
0.5
0
2
2
1
(d)
0.4
0.1
10
0.6
10
101010
10 10
0.3 0.3
0.2 0.2
10
0.8
0
00
0.70
0
0
10
VQRS
5
8
VQRS
0.2
0.3
6
Time [s]
VBaseline+DC
4
6
44 4
Time [s] 6 6 6
4 Time
4Time
[s][s] [s]6 6
Time
TimeTime
[s] [s]
0.6
0.4
4
Time [s]
0.8
0
10
3mm x 3mm
While DOU T provides an approximate
timing of the ECG
QFN-16 ECG ASIC
R-wave, an accurate ECG R-wave timing is necessary for
several cardiovascular monitoring applications such as the
ECG Electrode 2
calculation
of heart
rate variability
for disease prediction.
ECG Electrode
1
10 10
8
8
VQRS
VQRS
0.5
2
Time [s]
0
0.8
0000.8
0
00 0 00
0.700.70
0.6 0.6
1
10
10
10
10
DOUT [V]
[V][V]
D DOUT
OUT
Amp Outputs [V]
[V]
Outputs
Amp
[V]
DOUT
10
101010
TimeTime
[s] [s]
2
ECG Electrode 1
VBaseline+DC
VQRS
8
C. Recovering the ECG R-wave Timing from DOU T
VBaseline+DC
8
88 8
6
Time [s]
0
2
Amp Outputs [V]
2
4
0.1
0 0
0 0
DOUT [V]
Amp Outputs [V]
6
Time [s]
0
0.8
0000
000
0.7
10
10
10
10
4
2
[V]
D
OUT
Outputs
Amp
[V][V]
Outputs
Amp
DOUT
[V][V]
DOUT
10
10
0.1 0.1
0 0
2
10
10
0.8
0.8
Fig. 10. a) Measured chest ECG at rest (gain = 52dB), b) measured chest
ECG with baseline drift due to motion artifacts (gain = 52dB), c) measured
0 muscle noise and signal clipping (gain = 64dB), and d)
chest ECG with
0
2
4
6
8
measured head ECG with high gain due to attenuated
Time [s]signal (gain = 84dB).
0.2
0.6
Estimation of the R-wave timing using the midpoint timing of
0.5
0.4
0.3
0.2
0.7
0.4
0.2
0.6
5
10
15
20
25
30
35
40
0.4
0.3
0.1
45
19
19.1
DOUT [V]
5
10
15
20
25
30
35
1
Manual
0
5
10
15
20
25
30
Time [s]
35
40
35
40
0.1
45
19
19.1
19.1
19.2
19.1
19.2
19.2
1
5
10
15
20
5
10
15
20
25
30
25
30
35
40
Midpoint
Timing
0.5
0
45
19
19.1
19.2
19
19.1
19.2
1
Estimated
Manual
0.5
0
35
40
0.5
45
0
Time [s]
Time [s]
0
19
40 3mm
45 x 3mm
1
QFN-16 ECG ASIC
Estimated
30
1
Midpoint
Timing
0.5
25
3mm x 3mm
QFN-16 ECG ASIC
0.5
19.2
1
R-waves
0
20
0.2
1
0.5
15
1
R-waves
0
10
0.5
0
0.5
5
DOUT [V]
0.6
DOUT [V]
Amp Outputs [V]
Amp Outputs [V]
Although the R-wave’s peak is clipped in DOU T , the original R-wave timing can still be recovered with minimal error.
As shown by Fig. 12, the R-wave timing can be estimated
from the midpoint timing of DOU T pulses. This method is
ECG Electrode 2
ECG Electrode 1
tested on normal chest ECG records from ten subjects totaling
2,304 heartbeats from the MIT-BIH PhysioNet database and
V
V
Fig. 11. The wearable ASIC board at the head
with
wireless
data
transmission
from our MIT clinical test (MIT IRB approval #1104004449).
V
V
to a computer.
Midpoint estimated R-wave timings are compared with manually annotated timings, the results of which are summarized
In Fig. 10(c), pectoral muscle artifacts are present from in Table III.
a rapid horizontal 90◦ arm movement. Also, an intentional
high gain of 64dB increases the amplified ECG to 2.8Vpp ,
TABLE III
C OMPARISON BETWEEN MIDPOINT- ESTIMATED R- WAVE TIMINGS AND
which is beyond VDD = 0.8V and is clipped. To produce Midpoint
Timing
MANUALLY ANNOTATED R- WAVE TIMINGS FROM TEN SUBJECTS .
the correct DOU T , VDC needs to be increased to 0.5V so
that VBaseline+DC rises above VQRS ’s muscle artifacts and
Estimated
Manual
amplified T-waves. The QRS complex’s
clipping does not
Subject Number Mean
Stdev.
Sampling
of Beats R-wave
R-wave
Freq.
matter because the beat information is still present. This
Timing
Timing
[Hz]
scenario is an example of a significant change of measurement
Error [ms]
Error [ms]
condition leading to a new VDC setting.
1
250
0.91
1.6
250
To test the ASIC in the presence of an attenuated ECG
2
183
0.91
1.6
250
signal, we mount it at the head so that the ECG is measured
3
63
0.97
2.2
250
across the ear and the middle upper neck as shown in Fig. 11.
4
123
-1.70
1.6
250
The ECG at this location is in the range of 30µVpp − 40µVpp ,
5
73
-2.40
1.8
250
6
467
-1.50
0.71
500
which is two orders of magnitude smaller than the standard
7
363
-1.00
0.71
500
chest ECG. This attenuation is due to the pattern of the ECG
8
357
-2.80
0.72
500
field lines at the head, which yield a very small potential
9
226
-0.88
0.72
500
difference when projected onto the lead. Because of this
10
199
-0.29
0.84
500
attenuation, the head ECG has a poor signal-to-noise ratio and
Overall
2,304
-0.70
1.25
only R-waves are immediately visible [15].
0
0.8
DOUT [V]
0.5
0
19
45
Time [s]
ECG Electrode 2
ECG Electrode 1
1
VQRS
VBaseline+DC
10
5
10
1
0.5
15
Amp Outputs [V]
20
25
30
35
40
20
25
30
35
40
19.2
Midpoint
Timing
19
19.1
19.2
19
19.1
19.2
1
Manual
15
Estimated
20
25
30
35
40
45
0.5
0
0
5
10
15
20
0.5
0.4
0.3
0.2
25
30
35
40
0.1
45
19
19.1
19.2
19
19.1
19.2
19
19.1
19.2
1
DOUT [V]
1
0.5
0
0.6
Time [s]
Time [s]
DOUT [V]
10
19.1
0.5
0
45
0.2
5
19
1
0.4
Baseline+DC
0.7
Baseline+DC
QRS
0.3
0.1
45
0.6
15
0
QRS
0.5
0.4
5
10
15
20
25
30
35
40
0.5
0
45
1
1
R-waves
0
0.6
0.2
DOUT [V]
5
1
0.8
R-waves
0
0.5
Amp Outputs [V]
0.4
0.2
VBaseline+DC
0.7
1
0.6
Amp Outputs [V]
VQRS
0.8
R-waves
8
8
8
4
6
44 4
Time [s] 6 6 6
Time
Time
Time
[s][s] [s]
8
8
2 0.8
attenuation,
0.2
0.80
0.8
00.8
0.8
0.8 0.8
101010
10 10
10
10
101010
10 10
VBaseline+DC
6
6
6
6
Time [s]
Time [s]
Amp Outputs [V]
0.3
4
4
0.1
0
0
VQRS
2
22 2
2
2
DOUT [V]
10
101010
0.4
(b)
6
0
R-waves
8
88 8
VBaseline+DC
8
8
88 8
8 8
VQRS
4
4 Time [s]
Time [s]
0.1
10 0
Due0 to
0.3
0.8
0.8
0
0.2
0.70
0.7
0.1
0.6
0.6
0
0.5
0.5
0.4
0.8
0.4
0.3
0.3
0.2
0
0.2
0.10
Amp Outputs [V]
6
66 6
Time
Time
Time
[s][s] [s]
VQRS
6
VQRS
Time [s]
4
6
2
4
6
2 2 2 [s] 4 46
66 6
4
4 4 Time
2 2
4 46
6 6
Time [s]
Time
[s][s] [s]
Time
Time
[s]
Time [s] Time
TimeTime
[s] [s]
2
2
0.5
0.8
0.4
DOUT [V]
1010
0.8
0
0.2
0.8
00
0
0.1
0.7
0
0.6
Amp Outputs [V]
88
Time [s]
4
0.2
DOUT [V]
0.5 444 4Time [s]
2
222
0 0.80
0 0.8
0.8
0.80
8
888
2
66
Time[s][s]
Time
10
6
2
0
R-waves
2
V
8 Baseline+DC 10
V
6 QRS
[V][V]
D D [V][V]
D [V]
[V]
D
DDOUT
OUT
O
Amp
[V]
Outputs
Outputs
Amp
OUT
[V]
[V]
Outputs
Outputs
Amp
Amp
[V] D
[V] D D [V][V] Amp
Outputs
Outp
Amp
Amp
OUT
OUTOUT
[V]
Outputs
Outputs
Amp
Amp
[V] D[V]
DOUT
D[V]
[V][V] [V]
D
DOUT
[V][V] D
OUT
OUT
Amp
Amp
[V]Outputs [V]
Amp
Amp
[V][V]
[V]
Outputs
Outputs
Amp
Amp
OUT
OUTOutputs
[V][V]Outputs
Outputs
Outputs
Amp
Amp
[V] [V] DOUT
[V][V]Outputs [V]
Amp
Amp
DOUT
OUT
OUT
[V]
Outputs
[V]
[V]
D
[V]
[V]
DAmp
DD
[V] Outputs
[V] Outputs
Outputs
Outputs
Amp
Amp
OUT
OUT
OUT
Outputs[V][V]
AmpOutputs
Amp Outputs [V]
OUT
OUT
Outputs
Amp
Amp
[V] [V]
DOUT
Outputs[V][V]
AmpOutputs
Amp Outputs [V]
Amp
[V][V] D
DOUT
DOUT
[V]
[V]
DOUT
OUT
Amp Outputs [V]
2
22 2
10
101010
10 10
8
R-waves
10
10
4
4
0.6 4(a)
Time [s]
2
22
2
22
8
88 8
8 8
6
Time [s]
R-waves
8
10
1010
0
0.8
000444 4Time [s] 666 6
0 40 Time
4Time
[s][s] [s]6 6
Time
[s] [s]
0.7 TimeTime
4
0.5
0.4
0.4
0.3
0.3
0.8
0.2
0.2
0.7
0.1
0.1
0.6
0
0
0.5
0.8
0.4
0.8
0.3
4 gain is 6increased 8to 84dB to
10
the
the
Time [s]
sense the 30µVpp of ear ECG. At this high gain, a significant
portion of the amplified output is noise and R-wave clipping is
0
8
10
2 2.7dB. 4
6
present,
leading to an0 SNR of only
However, with
the
Time [s]
identical VDC setting as in Fig. 10(a) and 10(b), VBaseline+DC
VBaseline+DC
is able to rise above the noise and correctly capture the
8
10
heartbeats
as shown by DOU T in Fig. 10(d).
88
1010
10
101010
VBaseline+DC
VQRS
2
4
DOUT [V]
8
88
2
0.8
0.5
0.5
0.5
0.8
0 0.5
0.2
0.5
0 0.5
0.7
0.4
0.40.4
0.4
0.7
0.1
0.4 0.4
0.6
0.3
0.3
0.3
0.6
0 0.3
0.3
0.3
0.8
0.5
0.2
0.8
0.8
0.8
0.20.2
0.2
0.5
0.2 0.2
0.7
0.4
0.1
0.7
0.8
0.70.1
0.7
0.1
0.1
0.4
0.1
0.1
0.6
0.3
0 0.6
0.6
0.6
00 0
0.3
0.50 0
0.2
0.5
0.5
0.5
0
0.8
0.2
0
0.4
0.1
0.8
0.8
0.8
0.4
0.4
0.8
0.4
0.1 0.8
0.3
0 0.3
0.3
0.3
00
0.2
0000.2
0
0.2
0.8
0.2
00 00.8
00
0.8
0.10 0
0.8
0.10.1
0.7
0.1
0.7
0
0
0.6
0 00.6
0.8
0
0.50 0.5
0.8
0 0.8
0.8
0
0.8
0.7
0.4 0.4
0.6
0.3 0.3
0.8
0.8
0.8
0 0.8
0.5
0.8
0
0.2
0.7
0000.8
00.20
00.7
0.7
0.7
0.4
0.7
0.1 0.7
0.6
0.1
0.60.6
0.6
0.3
0.6
0 0.6
0.5
0
0.50.5
0.5
0.2
0.5 0.5
0.4
0.40.4
0.8
0.4
0.1
0.8
0.4 0.4
0.3
0.3
0.3
0 0.3
0.3
0.3
0.2
0.2
0.2
0 0.2
0.2
0
00.2
0.1
0.8
0.10.10
0.1
0.1
0 0.1
00 0
0 0
10
10
Baseline+DC
QRS
DOUT [V]
10
10
10
10
VBaseline+DC
VQRS
Amp Outputs [V]
8
888
2
22 2
2 2
DOUT [V]
[V][V]
Outputs
Amp
Outputs
Amp
Outputs
Amp
Amp
[V][V]
[V][V] [V]
[V][V] [V]
D
DOUT
DOUT
D
[V]
[V]
[V]
DD
DAmp
DD
[V]
Outputs[V]
AmpOutputs
[V][V]
Outputs
Outputs
OUT
OUT
Outputs
Outputs [V]
Amp
Amp
OUT
[V] DD D [V]
[V]
[V]
D
DOUT
D
[V]
Outputs
Amp Outputs [V]
OUT
OUT
OUT
[V][V] Amp
D D [V][V] Amp
[V]Outputs
[V]Outputs
Outputs
Amp
[V]
D
OUT
OUT
OUTOutputs
OUT
OUT
Outputs[V][V]
Amp
[V]
[V][V]
Amp
Amp
OUT
OUT
[V]
Outputs
Outputs
Amp
Amp
[V] D Amp
[V] DD
[V]
Outputs
Outputs
Amp
Amp
OUT
OUT
[V]
Outputs
Outputs
Amp
Amp
[V] D
DOUT[V][V] DAmp
[V][V] D[V]
DOUT
DOUT
[V]Outputs
[V][V]
OUT
OUT
[V]
Amp
Amp
[V]Outputs D
[V]Outputs [V]
Outputs
Amp
Amp
[V][V]
[V][V]
Outputs
Outputs
Amp
OUT
OUT
Outputs
Outputs
Amp
Amp
Amp
Amp
[V]
OUT
OUT
OUT
[V]
Amp
[V] OutputsD[V]
[V] Outputs [V]
Outputs
AmpOutputs
Amp Outputs
OUT
10
1010
DOUT [V]
8
88
Baseline+DC
QRS
0.80
0.8
0
0.8
[V][V] D
DOUT
[V]
[V]
DD
OUT
[V]
DOUT
OUT
OUT
10
1010
0.40.4
0.4
0.7
0.4 0.7
0.4
0.3
0.6
0.30.3
0.3
0.6
0.3 0.6
0.3
0.8
0.2
0.5
0.80.8
0.8
0.2
0.2
0.2
0.5
0.5
0.2
0.2
0.7
0.1 0.7
0.4
0.7
0.7
0.10.1
0.1
0.4
0.4
0.1
0.1
0.6
0 0.6
0.3
0.6
0.6
0 0 0.3
0
0.50 0.30
0.2
0.50.5
0.5
0.8
0.2
0.2
0.4
0.80.8
0.8
0.1
0.40.4
0.4
0.8
0.8
0.1
0.3 0.1
0.30.30
0.3
0 00
0.2
0000.2
0
0.2
0.8
0.2
00 00.8
00
0.100.80
0.8
0.8
0.10.1
0.7
0.1
0.7
0
0
0.6
0 00.6
0.8
0
0.5 0.8
0.8
000
0.8
0.5
0.8
0.70 0
0.80.8
0.8
0.4 0.7
0.7
0.7
0.4
0.6
0.3 0.6
0.6
0.8
0.6
0.3
0.8
0.8
0.8
0.5
0
0.8
0.8
0
0.2
0.5
0.7
0000.5
0.5
0.2
0
0
00.7
0.7
0.7
0.4
0.7
0.7
0.1 0.4
0.4
0.6
0.4
0.1
0.60.6
0.6
0.3
0.6
0.6
0 0.3
0.3
0.5
0.3
0
0.8
0.50.5
0.5
0.2
0.8
0.8
0.5 0.2
0.5
0.2
0.4
0.2
0.7
0.40.4
0.4
0.1
0.8
0.7
0.8
0.4 0.7
0.4
0.1
0.1
0.3
0.1
0.6
0.30.3
0.3
0
0.6
0.3 0.6
0.3
000
0.2
0.5
0.2
0.2
0.2
0.5
0.5
0
0.200.8
0.2
0.1
0.400
0.10.1
0.1
0.8
0.8
0.4
0.8
0.4
0.1
0.1
0 0.3
0 00.3
0
0 0.3
0
0.2
0
0.2
0.8 0.2
0000
0.8
0.80.8
0.8
0.1000
0.8 0.1
0.8
0.1
0.7
0
00
0.6
0
0.8
0.8
0000.8
0
00 00.5
00
0.8
0
0.700.8
0.7
0.4
0.6 0.6
0.3
0.8
0
0.5 0.8
0.8
0.8
0.5
0
00
0.2
0.7
00
0.4 0.7
0.7
0.7
0.4
0.1
0.6
0.3 0.6
0.6
0.6
0.3
0.50
0.2 0.5
0.5
0.5
0.2
0.4
0.1 0.4
0.4
0.8
0.4
0.1
0.3
0 0.3
0.3
0.3
0
0.2
0.2
0.2
0.2
0
0.1
0.8 0.80
0.1
0.1
0.1
0
000
10
3
10
2
10
[V][V] D
DOUT
[V]
[V]
DD
OUT
[V]
D
OUT
OUT
OUT
DOUT[V][V]
DOUT
1
10
Frequency [Hz]
Amp Outputs [V]
Input-referred
Noise
Input-referred Noise [V/(Hz)1/2]
-6
10
Amp Outputs [V]
[V]
D
OUT
Output
Amp
Outp
Amp
Amp Output
[V][V]
Outputs
Amp
Outputs
Amp
Amp Outputs [V]
Amp Outputs [V]
Total Gain [dB]
DOUT [V]
[V][V]
DOUT
DOUT
[V]
DOUT
DOUT [V]
0
10
0.5 0.8
0.50.5
0.5
0.8
0.5 0.8
0.5
0.4
0.7
R-waves
6
Bandwidth
-7
10
Amp Outputs [V]
6
Total Gain
20
10
DOUT [V]
6
0.7
0.70.7
0.7
0.6
0.60.6
0.6
0.5
100 0.5
0.5
0.5
90
0.4
0.40.4
0.4
80
0.3
0.30.3
70
0.3
0.2
60 0.2
0.2
0.2
50
0.1
0.10.1
0.1
40
0
30
00 0
R-waves
6
0.5
0.7
0.4
0.50
0.70.7
0.7
0.4
0.6
0.3
0.5
0.5
0.60.6
0.6
0.3
0.2
0.8
0.5
0.2
0.50.5
0.5
0.4
0.2
0.7
0.4
0.1
0.40.4
0.4
0.4
0.8
0.1
0.4
0.6
0.3
0 0.3
0.1
0.8
0.3
0.3
0
0.3
0.5
0.2
0.20.2
0.2
IEEE TRANSACTIONS
ON
BIOMEDICAL
CIRCUITS
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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
In all ten subjects, the standard deviation of R-wave timing
error is less than the sampling period. This demonstrates
that the R-wave midpoint estimation method can accurately
recover the ECG peak timing information from DOU T . This
enables the use of the ECG ASIC for applications beyond
heartbeat detection, such as heart rate variability analysis,
where accurate R-wave timing is necessary.
V. C ONCLUSION
An ECG ASIC for wearable heart monitoring is presented
that takes advantage of the ECG’s characteristics to extract
heartbeat timings in the presence of motion artifacts, muscle
noise, signal clipping, and attenuated ECG signals as low
as 30µV . Besides heartbeat detection, the R-wave timing is
extracted using a midpoint estimation method. R-wave timings
can be used for the calculation of predictive cardiovascular
parameters such as heart rate variability.
Implemented using a standard 0.18µm 1P6M CMOS technology, the ASIC consumes 58nW of power at 0.8V supply
and occupies 0.76mm2 of active die area. The ECG ASIC
has sufficiently low energy consumption for one year of
continuous operation from a 0.7mAh thin-film battery, making
it ideal for miniaturized and long term heartbeat monitoring in
extremely battery constrained applications such as implantable
pacemakers and defibrillators. Furthermore, the ECG ASIC’s
power consumption is in range of energy harvesting power
sources, thus making batteryless heartbeat monitoring a possibility.
7
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NY, USA: Wiley, 1996.
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of, vol. 44, no. 11, pp. 3030–3038, 2009.
[13] M. Miyahara et al., “A low-noise self-calibrating dynamic comparator
for high-speed ADCs,” in IEEE Asian Solid-State Circuits Conference,
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vital signs monitoring,” in IEEE Engineering in Medicine and Biology
Conference, 2010, pp. 6389–6392.
David Da He received the B.A.Sc. degree in electrical engineering from the University of Toronto in
2005, and the S.M. and the Ph.D. degrees in electrical engineering from the Massachusetts Institute of
Technology, in 2008 and 2013, respectively.
Dr. He has worked on a variety of sensors, including a wearable vital signs monitor, an organic
thin-film transistor temperature sensor, and industrial
wireless condition monitoring sensors. He has served
on the technical committee of the IEEE International
Conference on Body Sensor Networks. Currently,
Dr. He is a co-founder and the Chief Scientific Officer of Quanttus, where
he works on new ways for wearable sensors, algorithms, and data insights to
transform how we view personal health.
ACKNOWLEDGMENT
The authors would like to thank Professor Hae-Seung Lee
(MIT), Tom O’Dwyer (Analog Devices), and Dr. Michael
Coln (Analog Devices) for their valuable assistance. The chip
fabrication was generously provided by TSMC. This work
was funded by the MIT Medical Electronic Device Realization
Center (MEDRC).
R EFERENCES
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in the United States: a policy statement from the American Heart
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1324, 2007.
Charles G. Sodini received the B.S.E.E. degree
from Purdue University, in 1974, and the M.S.E.E.
and the Ph.D. degrees from the University of California, Berkeley, in 1981 and 1982, respectively.
He was a member of the technical staff at HewlettPackard Laboratories from 1974 to 1982, where
he worked on the design of MOS memory. He
joined the faculty of the Massachusetts Institute of
Technology, in 1983, where he is currently the LeBel
Professor of Electrical Engineering. His research
interests are focused on medical electronic systems
for monitoring and imaging. These systems require state-of-the-art mixed
signal integrated circuit and systems with extremely low energy dissipation.
He is the co-founder of the Medical Electronic Device Realization Center at
MIT.
Along with Prof. Roger T. Howe, he is a co-author of an undergraduate text
on integrated circuits and devices entitled ”Microelectronics: An Integrated
Approach.” He also studied the Hong Kong/South China electronics industry
in 1996-97 and has continued to study the globalization of the electronics
industry.
Dr. Sodini was a co-founder of SMaL Camera Technologies, a leader in
imaging technology for consumer digital still cameras and machine vision
cameras for automotive applications. He has served on a variety of IEEE
Conference Committees, including the International Electron Device Meeting
where he was the 1989 General Chairman. He has served on the IEEE Electron
Device Society Administrative Committee and was president of the IEEE
Solid-State Circuits Society from 2002-2004. He is currently the Chair of the
Executive Committee for the VLSI Symposia and a Fellow of the IEEE.
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A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing