Lab is open this week
 New lab hours
 Avoid overlap with ECE255 labs
 Monday 4pm – 6pm, Tuesday 3pm – 5pm
 Lab will open from today
 Each student will need to check out a Basys2 FPGA board
from the TA during lab hours
 Lab 1 will be announced today
 Lab 1 is due on 5pm, 2/9 Tuesday
 You need to work on your own
• No collaboration is allowed on ALL labs
 You need to have the TA to check off your code during the
lab hours
ECE 351 Digital Systems Design
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Announcement
 The pMods available for course project:
ECE 351 Digital Systems Design
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ECE 351
Digital Systems Design
VHDL Architecture, Packages,
and Data Types
Wei Gao
Spring 2016
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Recap of last class
 Digital logic review
 Boolean expressions using SOP/POS
 Combinatorial logic gates
 DeMorgan’s theorem
 Sequential logic & state machine
 VHDL overview
 Entity vs. architecture
 Port mode
 Signal values
ECE 351 Digital Systems Design
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Design Abstraction of Digital Systems
 At what level can we design?
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Design Abstraction of Digital Systems
 What does abstraction give us?
 The higher in abstraction we go, the more complex &
larger the system becomes
 But we pass over more details about how it performs
(hardware, speed, fine tuning, etc)
 Where is VHDL?
 System : Chip : Register : Gate
 Describe systems in two ways:
• Structural
• Behavioral
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VHDL Architecture
 An architecture is always associated with an entity
 Declared in the same file
 Entity specifies the external interfaces
 Architecture specifies the internal implementation
 Architecture declaration
 architecture-name
 entity-name
• The name of the entity that this architecture is associated with
• Must already be declared before compile
 Optional items
• types
• signals
: internal connections within architecture
• constants:
• functions
: calling predefined blocks
• processes
: calling predefined blocks
• components
: calling predefined blocks
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Architecture Syntax
architecture architecture-name of entity-name is
type…
signal…
constant…
function…
process…
component…
begin
…behavior or structure
end architecture architecture-name;
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“Hello-World” Examples
 Entity declaration
entity and2 is
port ( In1, In2 : in std_logic; Out1: out std_logic );
end and2;
 Architecture definition of an AND gate
architecture and2_arch of and2 is
begin
Out1 <= In1 and In2;
end architecture and2_arch;
Signal assignment
 Architecture definition of an ADDER
architecture adder_arch of adder is
begin
Out1 <= In1 + In2;
end architecture adder_arch;
Signal assignment
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VHDL Packages
 VHDL is a "Strong Type Cast" language…
 This means that assignments between different data types
are not allowed.
 This means that operators must be defined for given data
types.
 This becomes important when we think about synthesis
• For example: string + real = ???
- can we add a string to a real?
- what is a "string" in hardware?
- what is a "real" in hardware?
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VHDL Packages
 VHDL has built-in features:
 1) Data Types
 2) Operators
 Built-in is also called "pre-defined“
 Pre-defined functionality
 E.g.: there is a built in addition operator for integers
• integer + integer = integer
• The built-in operator "+" works for "integers" only
• It doesn't work for "bits" as is
 Other pre-defined operators?
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VHDL Packages
 Adding on functionality
 VHDL allows us to define our own data types and
operators
 A set of types, operators, functions, procedures… is called
a "Package“
 A set of packages are kept in a "Library"
 Analogy
 Built-in keywords/operators vs. customized functions in
C/C++
 Header files
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IEEE Packages
 When functionality is needed in VHDL, engineers
start creating add-ons using Packages
 When many packages exist to perform the same
function, keeping consistency becomes a problem
 IEEE publishes “standards" that give a consistent
technique for engineers to use in VHDL
 We include the IEEE Library at the beginning of VHDL code
• syntax:
library library-name
 We include the Package within the library that we want to
use
• syntax:
• all:
use library-name.package.function
use library-name.package.ALL
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Common IEEE Packages
 In the IEEE library, there are common Packages that
we use
 STD_LOGIC_1164
 STD_LOGIC_ARITH
 STD_LOGIC_SIGNED
library
use
use
use
IEEE;
IEEE.STD_LOGIC_1164.ALL;
IEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_SIGNED.ALL;
 Libraries are defined before the entity declaration
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Put it all together…
library IEEE;
use
use
use
IEEE.STD_LOGIC_1164.ALL;
IEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_SIGNED.ALL;
entity and2 is
port (In1, In2
Out1
end entity and2;
: in STD_LOGIC;
: out STD_LOGIC);
architecture and2_arch of and2 is
begin
Out1 <= In1 and In2;
end architecture and2_arch;
ECE 351 Digital Systems Design
-- package
-- entity declaration
-- architecture definition
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Another Example
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
entity inv1 is
port (In1
Out1
end entity inv1;
-- package
: in STD_LOGIC;
: out STD_LOGIC);
architecture inv1_arch of inv1 is
begin
Out1 <= not In1;
end architecture inv1_arch;
-- entity declaration
-- architecture definition
 The Pre-defined features of VHDL are kept in the STANDARD
library
 but we don't need to explicitly use the STANDARD library, it is automatic
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VHDL Signal
 A single bit is considered a Scalar quantity
 A bus (or multiple bits represented with one name) is
called a Vector
 In VHDL, we can define a signal bus as:
data_bus
or
data_bus
: in bit_vector (7 downto 0);
: in bit_vector (0 to 7);
 The Most Significant Bit (MSB) is ALWAYS on the left of
the range description:
 data_bus : in bit_vector (7 downto 0);
• data_bus(7) = MSB
 data_bus : in bit_vector (0 to 7);
• data_bus(0) = MSB
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VHDL Signal
 There are "Internal" and "External" signals
 Internal - are within the Entity's Interface
 External - are outside the Entity's Interface and connect it
to other systems
 Where do you declare internal and external signals?
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VHDL Data Types
 Scalar data types (built into VHDL)
 Scalar means that the type only has one value at any given
time
 Boolean: values TRUE or FALSE
• NOT 0 or 1!!!
 Character: values are all symbols in the 8-bit ISO8859-1 set
 Integer: the range comes from +/- 232
• 4 bytes for each integer
• What about C/C++?
 Real: values are fractional numbers from -1.0E308 to
+1.0E308
 Bit: values {'0', '1'}
• Used for logic gates
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VHDL Data Types
 Array Data Types (Built into VHDL)
 Bit vector
• Vector of bits, values {'0', '1'}
• Array values are represented with double quotes (i.e., "0010")
• This type can be used for logic gates: signal assignments
• First element of array has index=0
 String
• Vector of characters
Message
: string (1 to 10) := "message here…"
• First element in array has index=1
• E.g.:
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VHDL Data Types
 Physical Data Types (Built into VHDL)
 These types contain object value and units
 NOT synthesizable
 Time: the range comes from +/- 232
• Unit: fs, ps, ns, us, ms, sec, min, hr
 User-Defined Enumerated Types
 We can create our own descriptive types, useful for State
Machine
 No quotes needed
 E.g.:
type States is (Red, Yellow, Green);
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STD_LOGIC Data Types
 Within VHDL we only have BIT and BIT_VECTOR to model
logic gates
 These don't work for the real world
 We need to use the IEEE.STD_LOGIC_1164.ALL package
 STD_LOGIC:
 "resolved" data type, scalar (analogous to BIT, but with drive
strength)
 STD_LOGIC_VECTOR:
 "resolved" data type, vector (analogous to BIT_VECTOR, but
with drive strength)
 Recall our entity declaration…
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Summary
 Architecture
 Implementation of entities
 Optional items
 Packages
 Adding-on functionality
 IEEE packages: standards
 Data types





Scalar
Array
Physical
User-defined
STD_LOGIC
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Reading
 Textbook 2.1 – 2.4
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Announcement of Lab 1
 Get familiar with the ISE Webpack and ADEPT Software
 Get familiar with the programming process
 Write VHDL code, implement on Basys2 board, and verify
correctness for the (7,4) Hamming code.
 Denote the bit-locations left to right in the Hamming (7,4) code
by 1 to 7. In a Hamming code, the parity bits are placed at
locations 2n for n=0,1,2,3,…
 Use Basys2 board switches 7-1 to input data/parity bits, use
SW0for input enc, and use LEDs 2-0 to display computed parity
bits
 Further extend your (7,4) Hamming encoder/decoder to
use a 7-segment display on the Basys2 board to display
the location of an error in the decode-mode
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Announcement of Lab 1
 WEBPACK in the lab
 The computers in the lab have both WEBPACK v14.1 and
v13.2 installed
 The newest version (v14.7) online is compatible with the
v14.1 version on lab computers
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