Engineering 43
Sequential
(FlipFlop) Logic
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
But First… WhiteBoard Work
 For the Truth Table
Shown at right
• Construct the Karnaugh
Map
• Write The Minimized
Function Q(A,B,C,D)
• Draw the Logic Circuit
 Notice “1’s” in Rows
• 1, 5, 9, 13, 14, 15
– Need only put “1’s” in these
locations; other cells
Assumed to be Zero
Engineering-43: Engineering Circuit Analysis
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Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Q
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
Blank Map (NonStretching)
 Can TYPE in these Maps
AB\CD 00
01
11
00
01
11
10
00
A’B’C’D’
A’B’C’D
A’B’CD
A’B’CD’
01
A’BC’D’
A’BC’D
A’BCD
A’BCD’
11
11
ABC’D’
ABC’D
ABCD
ABCD’
10
10
AB’C’D’
AB’C’D
AB’CD
AB’CD’
00
01
1
2
Engineering-43: Engineering Circuit Analysis
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10 AB\CD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Stretchable Blank Map (by Hand)
Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Engineering-43: Engineering Circuit Analysis
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Q
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
AB\CD 00
01
11
00
01
11
10
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
10
New Subj: NAND Gate Synthesis
 Implement Arbitrary SOP Logic Fcn in
NAND Gates Only
• Check that Fcn can be placed in K-Map by
putting Expression in CANONICAL form
• Minimize the K-Map if possible
• Use Inverter Made from NAND gate if
needed (if only Positive InPuts Available)
• Invert entire Fcn Twice such that DeMorgan
to converts the SOP to Nest-of-NANDS
• Check by Inverting a second time
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
De Morgan’s Laws
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND Gate Synthesis PreReq
 Assume that ALL Inputs are available
ONLY in the HI, or 1, form.
 If 0 needed use NAND-Based inverter:
A
Engineering-43: Engineering Circuit Analysis
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A
0
1
B
B
1
0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
More… WhiteBoard Work
 Implement This New EXAMPLE
Function using ONLY NAND Gates
F  AC D  A B C D  A B
 An Example of NAND-Gate Synthesis
• NANDS are easier to construct than
ANDs, ORs, NORs
– NANDs are the preferred gate for logic circuits
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND Synthesis
1. Use The Truth Table and Karnaugh Map to
find the AND/OR minimized Product of
Sums (PoS) Boolean Logic; Equation;
e.g.: 𝐹 = 𝐴 ∙ 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐵 ∙ 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐵 =
𝐴∙𝐶∙𝐷+𝐵∙𝐷
2. NOT (invert) both sides of the logic
Equation; e.g.: 𝐹 =
𝐴∙𝐶∙𝐷 + 𝐵∙𝐷
3. Apply DeMorgan’s Theorem
(𝑃 + 𝑄 = 𝑃 ∙ 𝑄) to “NAND” the R.H.S
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND Synthesis
3. (cont.) Thus in the example:
𝐹 = 𝐴∙𝐶∙𝐷 ∙ 𝐵∙𝐷
•
The individual Factors are now NANDS
•
Thus have an AND of NANDS
4. Finally NOT both sides again to:
• Recover F on L.H.S.
• Convert the AND to a NAND on R.H.S
Or: 𝐹 = 𝐹 =
Engineering-43: Engineering Circuit Analysis
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𝐴∙𝐶∙𝐷 ∙ 𝐵∙𝐷
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
“Memory Filled” Logic
 The Invert/AND/OR Combinatorial
Logic Circuits depended ONLY on the
Current Inputs; previous states did Not
affect the Current State
• Combinatorial Logic is MemoryLESS
 In SEQUENTIAL Logic the Circuit
Output CAN Depend on the Previous
condition of the Circuit
• Sequential Logic is MemoryFUL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Sequential Circuit
Combinational
outputs
 A sequential circuit
consists of a
Combinational
feedback path,
logic
and employs
some memory
elements
External inputs
Memory outputs
Memory
elements
 [Sequential circuit] = [Combinational
logic] + [Memory Elements]
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Synchronous vs Asynchronous
 Almost all Logic “Chips” Include a Clock
 The Clock helps to “Synchronize” the
Operation of the Circuits.
 The “Clock” is simply a very regular Hi/Lo
Pulse train 
 Logic Forms are divided into two groups:
• SYNCHRONUS → Depend on Clock
• Asynchronous → NO Clock-Dependency
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NOR → any HI = LO, else Hi
Asynchronous S-R FlipFlop
 Cross-coupled NOR gates
R
Q
R
S
1
0
Q
Reset
S
[R,S] =[0,0] → [R’,S’] =[1,1]
Q'
1
0
• Similar to inverter pair, with capability to force
Q = 0 ([S,R]=[0,1]) or Q = 1 ([S,R]=[1,0])
0
R
1
Q
R
0
Set
Q'
S
1
0
R
1
S
Q'
0
n-1
??
Q
UnDet
Memory
Engineering-43: Engineering Circuit Analysis
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n-1
Q
S
Q'
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
??
NAND → any LO = HI, else Lo
NAND based SR FlipFlop
 Cross-Coupled NAND gates
S'
R'
Q
[R,S] =[0,0] → [R’,S’] =[1,1]
S'
Q
R'
Q'
• Similar to inverter pair, with capability to force
Q = 0 ([S,R]=[0,1]) or Q = 1 ([S,R]=[1,0])
NOR notes
NAND notes
 Any HI input → LO output
 Any LO input → HI output
• Any HI → LO
 All LO inputs → HI output
• All LO → HI (else HI)
Engineering-43: Engineering Circuit Analysis
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• Any LO → HI
 All HI inputs → LO output
• All HI → LO (else LO)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
State Behavior of SR FlipFlop
 Transition (NOT
Truth) Table
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Qn-1
0
1
0
1
0
1
0
1
Qn
0 hold
1
0 reset
0
1 set
1
X not allowed
X
characteristic equation
Qn = S∙ R’ + R’∙Qn-1
R
Q
Q'
S
NOR: Any “1” forces a “0”
Qn-1\SR 00
01
11
10
0
0
0
X
1
1
1
0
X
1
REset
SET
 Sequential (output depends on history
when inputs R=0, S=0) but asynchronous
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NOR SR FlipFlop Timing
R
Q
 Any HI input → LO output
Q'
 All LO inputs → HI output
S
• Any HI → LO
• All LO → HI
Qn = R’∙(S + Qn-1)
Reset
Hold
Set
Reset
Set
Race
100
R
S
Q
Q’
 “Races” Produce UnPredictable OutPuts
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Clocked SR FlipFlop
R'
 Control times when
enable'
R and S
S'
inputs matter
NOR: Any “1” forces a “0”
R
Q
S
• Otherwise, the slightest glitch on R or S while
enable is low could cause change in value stored
• Ensure R & S stable before utilized (to avoid
transient R=1, S=1)
Set
100
Reset
S'
R'
enable'
Q
Q'
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Q'
NOR → any HI = LO, else Hi
Clocked SR FlipFlops
 NOR-NOR
Implementation
R'
enable'
S'
 Truth
Table
R’
0
0
1
1
x
R
S
S’ En’ R S
Qn
0 0 1 1 NotAllowed
1 0 1 0 Reset to 0
0 0 0 1
Set to 1
1 x 0 0
Qn−1
x 1 0 0
Qn−1
x → Don’t Care
• For NOR: any-Hi→LO; ALL-LO→Hi
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Q
Q'
Clocked SR FlipFlops
 AND-NOR
Implementation
• AND: any-0 → 0
• NOR: any-1 → 0
 Truth
Table
R
0
0
1
1
x
S C
Qn
0 x
Qn−1
1 1
Set to 1
0 1 Reset to 0
1 1 NotAllowed
x 0
Qn−1
x → Don’t Care
Engineering-43: Engineering Circuit Analysis
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Circuit Symbol
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
SR FlipFlop Clock-Overide
 Sometimes Need to Set or Reset the
FlipFlop withOUT Regard to the Clock
OR: Any “1” forces a “1” (toggle armed)
 Note the position of Pr & Cl on the
3rd-Stage ORs (any Hi→Hi)
• Ensures Pr & Cl OverRide R, S, & C
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Edge Triggered D FlipFlop
 sensitive to
inputs only
near edge of
clock signal
(not while
steady )
NOR: Any “1” forces a “0” (toggle armed)
D’
D
holds D' when
clock goes low
0
R
Q
Clk=1
Q’
S
0
D
Engineering-43: Engineering Circuit Analysis
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D’
holds D when
clock goes low
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Edge-Triggered FlipFlop Flavors
 POSITIVE edge-triggered flip-flops
• Inputs sampled on RISING edge; outputs change
just after the RISING edge
 NEGATIVE edge-triggered flip-flops
• Inputs sampled on falling edge; outputs change
just after the falling edge
100
 D=0  Reset
D
 D=1  Set
CLK
Qpos
Qpos'
Qneg
Qneg'
Engineering-43: Engineering Circuit Analysis
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positive edge-triggered FF
negative edge-triggered FF
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND → any LO = HI, else Lo
Edge Triggered D FlipFlop
 4-NAND,
1-NOT
implementation
 Truth Table for
All Postive-Going
Edge D-FF’s
• NAND:
– any LO → Hi
– All HI → LO
Engineering-43: Engineering Circuit Analysis
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CLK
0
1
↑
↑
D Qn
x Qn−1
x Qn−1
0 0
1 1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Edge Triggered JK FlipFlop
 A “Toggling” Flip Flop
• Under a certain Control-Set: Q → Q’
– Notice that Q does NOT go HI-for-sure or
LO-for-sure, and it does NOT remain STEADY
 A NAND Nest:
• Circuit Symbol
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
JK FlipFlop Toggle TruthTable
 The Simplified Ckt
 ReCall NAND
• Any LO → Hi
• ALL Hi → LO
 Note that the
outputs feed back to
the enabling NAND
gates. This is what
gives the toggling
action when J=K=1
Engineering-43: Engineering Circuit Analysis
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C
0
1
↓
↓
↓
↓
J
x
x
0
0
1
1
K Qn
Notes
x Qn−1
No Chg
x Qn−1
No Chg
0 Qn−1
No Chg
1
0
Reset to 0
0
1
Set to 1
1 Q’n−1 TOGGLE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Cascading FF → Shift Register
 Serial-in/Parallel-out Shift register
• New value goes into first stage
• While previous value of 1st stg goes into 2nd stg
• The QN can be SAMPLED any time
Q0
IN
D Q
Q1
D Q
OUT
100
CLK
IN
Q0
Q1
CLK
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Example: Eliminate Inconsistency
Want to Send
SAME
Input Value
to
TWO Places
Using
Q0 & Q1
Clocked
Synchronous
System
Async
Input
D Q
Synchronizer
Q0
Async
Input
D Q
Clock
Clock
D Q
Q1
Q0
Q1
Clock
INput
is asynchronous and
fans out to D0 and D1
one FF catches the
signal, one does not
inconsistent state may
be reached!
CLK
Engineering-43: Engineering Circuit Analysis
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Q1
D Q
Clock
In
Q0
D Q
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
FlipFlops Summarized
 Development of D-FF
• Level-sensitive used in custom integrated
circuits
– can be made with 4 pairs of gates
– Usually follows multiphase non-overlapping
clock discipline
• Edge-triggered used in programmable logic
devices
– Good choice for data storage register
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
FlipFlops Summarized
 Historically the J-K FlipFlop was popular
but now never used
• Similar to R-S but with 1-1 being used to
toggle output (complement state)
• Same Operation Can always be
implemented using D FlipFlops
 Preset and Clear inputs are highly
desirable on FlipFlops
• Used at start-up or to reset system to a
known state
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
FlipFlops Summarized
 Reset (set state to 0)  R
• Synchronous: Dnew = R' • Dold
– Transition only when next clock edge arrives
• Asynchronous: doesn't wait for clock
– quick but dangerous by “Race” Possibilities
 Preset or Set (set state to 1)  S
• Synchronous: Dnew = Dold + S
– Transition only when next clock edge arrives
• Asynchronous: doesn't wait for clock
– quick but dangerous by “Race” Possibilities
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
WhiteBoard Work
 Use Gates and a
D-FF to Implement
the JK-FF operation
C
0
1
↓
↓
↓
↓
Engineering-43: Engineering Circuit Analysis
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J
x
x
0
0
1
1
K Qn
Notes
x Qn−1
No Chg
x Qn−1
No Chg
0 Qn−1
No Chg
1
0
Reset to 0
0
1
Set to 1
1 Q’n−1 TOGGLE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
All Done for Today
IEEE
91-1984
Gates
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering 43
Appendix
Logic Syn
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND Gate Synthesis PreReq
 Assume that ALL Inputs are available
ONLY in the HI, or 1, form.
 If 0 needed use NAND-Based inverter:
A
Engineering-43: Engineering Circuit Analysis
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A
0
1
B
B
1
0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
NAND Gate Synthesis
 With the expression in SOP form
1. After any needed inversions (using NAND
inverter); In the first logic level there are as
many logic gates as terms in the SOP
expression
2. Each gate corresponds to a SINGLE Term,
and has, as inputs, the variables in that term
3. The outputs of the First Logic-Level are ALL
inputs to a SINGLE (multi-input if needed)
NAND gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
F is an ARBITRARY Example as
Previously
Set by the logic Designer
Bruce Mayer, PE
Engineering-43: Engineering
Circuit Analysis
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BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
R
S
R
Q
S
Q
[R,S] =[0,0] → [R’,S’] =[1,1]
Engineering-43: Engineering Circuit Analysis
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0
Q
Reset
[R,S] =[0,0] → [R’,S’] =[1,1]
S'
R'
1
Q'
1
0
S'
Q
R'
Q'
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx