Electronics for a Telemetric Brain
Electrode Array System
by
Jan Mal'sek
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
At the Massachusetts Institute of Technology
May 14, 2002
©2002 Massachusetts Institute of Technology. All rights reserved.
Author
ience
Department of Electria Tngineering and Compu
May 14, 2002
Certified by
Professor Ian W. Hunter
Professor of Mechanical Engineering and Professor of BioEngineering
Thesis Supervisor
Accepted by
Arthur C. Smith
Chairman, Department Committee on Graduate Theses
1MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
JUL 3 1 2002
LIBRARIES
2
Electronics for a Telemetric Brain Electrode Array System
by
Jan Malisek
Submitted to the Department of Electrical Engineering and Computer Science
May 14, 2002
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
Abstract
The Telemetric Electrode Array System (TEAS) is a surgically implantable device for
studying neural activity in the brain. An eight-by-eight array of needles collects intracortical neural signals for the electronics system to process and wirelessly transfer to an
external recording system; the waveforms can then be analyzed to provide insight about
information processing in the brain. We have designed an analog front end that amplifies
the microvolt level signals before they are digitized with 12 bits of resolution at 31 kHz
per channel. A digital subsection performs peak detection on the sixty-four channels to
compress data before sending them over a Bluetooth-based radio link at 725 kbit per
second. The individual sections of the system have been designed and tested, but a fully
integrated and implantable version has not been implemented due to time constraints.
Thesis Supervisor: Ian W. Hunter
Title: Professor of Mechanical Engineering and Professor of BioEngineering
3
Acknowledgements
I am grateful to the other members of the TEAS team, without whom a project of this
magnitude could not be undertaken. In particular, Johann Burgert was a great teammate
for designing the electronics and a good sport for letting me do the digital section, which
is obviously so much cooler than the analog electronics and wireless link. Tim Fofonoff
and Bobby Dyer contributed pictures and diagrams to this paper, and they generally
contributed to the entertaining atmosphere in lab. They also built the actual electrode
array (with help from Colette Wiseman and Marie-Maude de Denus Baillangeon). A
bunch of Canadians (Martin Labrecque, Fedor Danilenko, and Thor Bjarnason) helped
get the Bluetooth module up to speed and worked on the wireless charging system. The
Brown University people (Nicho Hatsopoulos, Misha Serruya, and John Donoghue) made
our lives difficult by giving us the specifications we needed to achieve, but they provided
ample support (including seats during the 10-hour surgery in which they stood and
implanted our thing). John Ankcorn and the ORnet people at LCS were very helpful,
especially given that they were not involved in the project. I'd also like to thank the
people who proofread and gave me feedback on this document, especially Johann, Peter
Madden, Candice Kamachi, and Sylvain Martel. And, of, course, I'd like to thank
Sylvain and Ian Hunter for making it possible for me to work on such an exciting project.
4
Contents
Abstract ...............................................................................................................................
3
Acknow ledgem ents......................................................................................................
4
Contents ..............................................................................................................................
5
List of Figures .....................................................................................................................
7
List of Tables ......................................................................................................................
8
1. Introduction....................................................................................................................
9
2. TEA S System Overview ..............................................................................................
13
The Electrode Array...................................................................................................
13
Flexible PCB .................................................................................................................
15
Electronics System .....................................................................................................
18
Analog Electronics................................................................................................
18
Bluetooth W ireless Com m unication M odule.........................................................
20
D igital Electronics ...............................................................................................
21
Pow er System ............................................................................................................
22
3. D igital Electronics D esign .......................................................................................
24
H igh-Level D esign Choices.......................................................................................
24
The H igh-Speed Processor A lternative..................................................................
24
The Parallel H ardw are A lternative ........................................................................
26
Compression Considerations ...............................................................................
27
Breaking Up the D igital Section................................................................................
29
The Program m able Logic System ..............................................................................
32
Choosing Components, Part 1: Programmable Logic Device Selection ...............
32
Choosing Components, Part 2: Transmit Buffer SRAM and Ring Buffer SRAM... 34
AD C Interface.......................................................................................................
35
Spike D etection System .........................................................................................
40
Transm it Buffer Control ........................................................................................
47
Unifying the Programmable Logic Modules: the Global Counter........................
49
The M icrocontroller ..................................................................................................
FPGA Configuration.................................................................................................
5
51
52
4. Prototypes and Results.............................................................................................
56
December 2001 Array Implant .................................................................................
56
D igital P rototyp e ...........................................................................................................
63
The Rest of TEA S ......................................................................................................
69
5 . C on clu sion ...................................................................................................................
71
R eferen ces .........................................................................................................................
75
Appendix A: VHDL Code .............................................................................................
77
Appendix Al: Spike Detection System VHDL Source: ringbuf.vhdl .......................
77
Appendix A2: Transmit Buffer Control VHDL Source: bigbuf.vhdl.......................
86
Appendix A3: ADC Serial Interface Input Control VHDL Source: serin.vhd.......... 89
Appendix A4: ADC Serial Interface Output Control VHDL Source: serout.vhd ........ 91
Appendix A5: Global Counter VHDL Source: cntr.vhd ..........................................
93
Appendix A6: TEAS Integration VHDL Source: teas.vhd........................................
94
Appendix B: Microcontroller Code to Configure FPGA...............................................
97
Appendix C: Java Source for FPGA Configuration File Compression..........................
102
Appendix C l: readbin.java .........................................................................................
102
Appendix C2: FileIO .java...........................................................................................
104
Appendix C3: BadFilenameException.java................................................................
106
Appendix Dl: BGA ZIF Socket Pinout..........................................................................
107
6
List of Figures
Figure 1: A Macaque monkey's skull is not much bigger than a computer mouse. ......... 10
Figure 2: Example 32-sample neural signals from existing tethered system, sampled at 20
kH z ............................................................................................................................
Figure 3: Major TEAS components, broken up by location of implantation. ..............
11
13
Figure 4: Electrode array after being machined from titanium block (photos by Tim
F o fono ff ) ..................................................................................................................
14
Figure 5: Electrode array assembly steps (drawing by Bobby Dyer and Tim Fofonoft). 15
Figure 6: Flexible printed circuit layout. .......................................................................
16
Figure 7: Flexible PCB detail around electrode array footprint. ..................................
16
Figure 8: Flexible PCB and 80-pin connector. The electrode array is soldered into the
holes on the left side of the PCB, which has laser cuts between traces to make it
more flex ib le.............................................................................................................
17
Figure 9: Electronics system block diagram. The analog section consists of 64 amplifiers
and 8 ADCs; the digital section, made up of an FPGA, two SRAMs, and a
microcontroller, processes the data from the ADCs and sends captured neural
waveforms to the Bluetooth wireless interface......................................................
18
Figure 10: Single channel of analog amplifier.............................................................
19
Figure 11: Digital electronics block diagram ................................................................
22
Figure 12: Abstraction and hierarchy in the TEAS electronics design.........................
30
Figure 13: The FPGA is one of the largest components in the design. ........................
34
Figure 14: ADC interface timing diagram for reading one sample. .............................
36
Figure 15: ADC interface timing for reading a sample every 16 clock cycles.............
36
Figure 16: Initial, highly parallel ADC interface block diagram..................................
37
Figure 17: Final ADC interface block diagram . ............................................................
39
Figure 18: Prestore, threshold, and poststore on a typical neural spike waveform. ......... 41
Figure 19: Spike detection system SRAM organization...................................................
42
Figure 20: STATUS variable bit descriptions. ...........................................................
43
Figure 21: Spike detection system state diagram.........................................................
46
7
Figure 22: Timing of data transfer between spike detection and transmit buffer SRAMs.
...................................................................................................................................
48
Figure 23: The 33-bit global counter. ............................................................................
49
Figure 24: FPGA passive serial (PS) configuration circuit. .........................................
53
Figure 25: FPGA passive serial (PS) configuration timing diagram. ............................
54
Figure 27: Adapter module for December 2001 implant (photo by Bobby Dyer). The
right end connects to the flexible PCB; the black Omnetics connectors are on the
left. ............................................................................................................................
57
Figure 28: Test electrode array for December 2001 implant (photo by Tim Fofonoff). .. 58
Figure 29: Surgeons attempt to permanently deform flexible PCB to conform to skull.. 59
Figure 30: The flexible PCB is tacked down to the skull with an acrylic adhesive before
the electrode array is inserted in the brain. ...........................................................
60
Figure 31: The electrode array, about to be inserted into the brain with a pneumatic
insertion too l. ............................................................................................................
61
Figure 32: The entire assembly is covered with an acrylic adhesive.............................
62
Figure 33: Component placement on the digital prototype. The PCB and component
outlines are show n actual size...............................................................................
64
Figure 34: Layout of top layer of digital prototype PCB...............................................
65
Figure 35: Layout of bottom layer of digital prototype PCB........................................
66
Figure 36: The fully assembled digital prototype..........................................................
67
Figure 37: Logic analyzer screen shot showing ADC serial clock and eight serial control
signals staggered by 2 clock cycles. ....................................................................
68
Figure 38: The digital prototype is not ready for implanting, yet..................................
69
Figure 39: Neural simulator circuits used to test amplifier circuit. ..............................
70
Figure 40: BG A ZIF socket pinout.................................................................................
107
List of Tables
Table 1: Power budget for TEAS electronics, assuming a 3.0 V power supply........... 23
8
1. Introduction
For the past decade, neurophysiologists have studied the brain using multichannel electrode arrays inserted directly into the brain. The small size of the electrodes
allows researchers to observe the electrical behavior of very small clusters of neurons and
possibly the activities of individual neurons.
Because of this high resolution, the
electrode arrays could potentially be used in human-machine interfaces that connect
directly to the brain. The notion of a brain-machine interface is not new, and even noninvasive attempts based on electroencephalograph (EEG) readings have yielded limited
successI; however, such non-invasive techniques generally measure the low-frequency
aggregate activity of large regions of the brain and thus do not provide the
communication bandwidth necessary for a practical interface 2 . Studies with existing
electrode arrays have indicated that only a few dozen electrode waveforms are sufficient
for prediction of a monkey's arm motion 3 , and the arrays could theoretically have
hundreds or even thousands of electrodes. Human-machine interfaces based on such
arrays would have the advantage of not requiring conscious thought, thus presenting
users with the ultimate in usability: operating a brain-interfaced device would be no
different from operating one's limbs. One of the first practical applications could indeed
involve electronically bypassing injured spinal cords to restore muscle control in
paraplegics.
Much neurological research is still necessary before the ultimate goal of a
practical brain-machine interface is realized.
An important step in advancing that
research is to develop better equipment and experimental processes. Current electrode
arrays require substantial support electronics outside of the skull for amplifying and
recording neural waveforms 4 . The external electronics must be tethered to the Macaque
monkeys on which experiments are typically performed; the monkeys must then be
restrained to prevent disconnection from the data acquisition system (and to keep the
monkeys from chewing through the cables). Because there is a direct, physical link from
the inside of the skull to the outside system, some wire or connector must protrude
through the skin, creating a potential for infection in the monkey.
The goal of the Telemetric Electrode Array System (TEAS) 5 is to create a
9
completely implantable, wireless system that will solve the problems with current,
tethered electrode arrays. The system will be used by Brown University neuroscientists,
who also specified most of the necessary design parameters. All electronics must fit
within a 50 mm x 50 mm x 10 mm case that will be implanted outside the skull but under
the skin. Figure 1 shows that the back of the monkey's skull, where the electronics will
be located, is about as large as the back of a computer mouse. A flexible printed circuit
will connect a custom, 64-electrode array to the electronics.
A battery and wireless
charging system can be implanted in the abdomen of the monkey and thus do not
contribute to the size of the main acquisition and control electronics on the skull.
To limit development time and cost, a primary initial requirement for the
electronics system was that it had to be made using only commercial, off-the-shelf
(COTS) components. This requirement, together with the small size requirement, has
had a substantial impact on the design and on the problems encountered.
A very
preliminary high-level design was made to determine the general types of components
required, and then a substantial amount of time was spent searching for the smallest
Figure 1: A Macaque monkey's skull is not much bigger than a computer mouse.
10
available components with the desired specifications. The final design was then crafted
around the components we could obtain. The implant would certainly be substantially
smaller if everything were built into a custom integrated circuit, but the current TEAS
design should fit within the available space limit.
The neural signals that TEAS must measure are the microvolt outputs of
individual neurons.
The electrode array is inserted in the general area of the motor
cortex, but there is no control over the final position of the electrode tips relative to
individual neurons.
The tips therefore pick up the signals of whichever neurons are
closest, and some electrodes will pick up good signals while others will not. A wellpositioned electrode should pick up signals that are about 100 pV peak-to-peak. Monkey
neurons fire approximately 1.5 ms spikes at 10-300 Hz 4 . A few sample spikes taken by
the existing data acquisition system are shown in Figure 2. The voltage typically drops
60
50
40
30
20
10
0 0
-20-30-40-50
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Time (ms)
Figure 2: Example 32-sample neural signals from existing tethered system, sampled at 20 kHz.
11
quickly, then rises above the idle level, and then returns more slowly to the starting
voltage. The voltage is roughly constant between spikes, and the details of the inactive
portion of the neural signal are not interesting to the TEAS users.
For the system to be useful, the TEAS electronics must digitize the analog neural
signals with twelve bits of resolution; the end users also want a minimum sampling rate
of 30 kHz. Therefore, transmitting just the raw data for all 64 channels, without any
communication protocol overhead, would require a 23 Mbps wireless connection.
Fortunately, the Brown scientists are interested only in the timing and shapes of the
approximately 1.5-ms-long neural spikes discussed above. Since the average spiking rate
is low, transmitting only the spikes reduces the bandwidth requirements by a factor of
fifty and makes the bandwidth requirement a more reasonable 500 kbps, again not
including any communications overhead. However, the electronics in the implant must
then perform some form of triggering and present a more complicated user interface that
allows the user to set the threshold and other peak detection parameters.
The TEAS electronics system will thus essentially be a 64-channel, wireless
oscilloscope that must be small enough to implant in a small monkey's head.
The
conflicting "64-channel" and "small, but with off-the-shelf components" requirements
made the design especially difficult. A large portion of the area on the final printed
circuit board will be taken up by amplifier circuits that are replicated 64 times since the
neural signals are too weak to multiplex without amplifying them first. Running 64
channels also complicates the digital portion of the system, which must perform peak
detection on 64 independent channels. The rest of this document will describe the details
of the TEAS electronics system design, present preliminary results, and indicate the
current status and future direction of the project.
12
2. TEAS System Overview
The entire TEAS system is a large project that does not involve electronics alone,
and it is therefore being designed and built by many members of the TEAS team; even
the electronics work is large enough of a task that it is being done by two individuals.
Before jumping into the digital electronics section, it is necessary to briefly describe all
the parts of the system and how they are interconnected.
A block diagram of the four major components of TEAS, broken up by location
of implantation within the test subject, is shown in Figure 3. The square, eight-by-eight
electrode array is inserted into the motor cortex of the brain. Most of the electronics
reside in the main unit implanted on the head. The electronics are mounted to the outside
of the skull, and they are connected to the array on the inside through a flexible printed
circuit board that contains sixty-four thin traces. The cable must be flexible enough to
allow the electrode array to move independently of the rest of the electronics and stay
implanted in the brain, which moves within the skull. The only electronics not on the
skull are the battery and wireless charging system, which can be implanted in the
abdomen of the monkey.
64-ELECTRODE
ARRAY
MOUNTED
ELECTRONICS
ECYTEMIC
SYSTE M
FLEXIBLE PCB
---
BATTERY AND
CHARGING
SYSTEM
Figure 3: Major TEAS components, broken up by location of implantation.
The Electrode Array
The electrode array 6 is a critical part of TEAS because it is the physical interface
between the electronics and the brain.
While designing and building the array is
primarily a mechanical engineering challenge undertaken by other members of the TEAS
team, some understanding of the array is important to the appreciation of the entire TEAS
project.
Furthermore, the electrodes are particularly significant to the electronics
designers because they are effectively electronic components.
13
Because the array is
connected to the electronics using flexible printed circuit board technology, a
combination of mechanical and electrical engineering techniques is necessary to achieve
the effective brain-electrode and electrode-electronics interfaces that are crucial to the
success of TEAS.
The electrode array is an 8 x 8 array of 1-mm-long electrodes that are 80 Am wide
and spaced 508 Am apart. Each electrode is electrically insulated except at its platinumcoated tip, which serves as the electrical contact point to the brain. The array is cut out of
Figure 4: Electrode array after being machined from titanium block (photos by Tim Fofonoff).
a solid piece of titanium using wire electrical discharge machining (wire EDM). Two
cutting passes are made with a 90-degree rotation between passes, resulting in electrodes
with a square cross-section, as shown in Figure 4. The electrodes are then coated with
gold and secured to a polyimide substrate before being cut off from the titanium base,
again using wire EDM. At this point, the electrodes are electrically isolated but held in
position by the polyimide.
The array is then soldered to a flexible PCB (described
below), which provides additional rigidity and electrical contacts to individual electrodes.
The entire assembly is then coated in parylene, a biocompatible insulator. The parylene
is removed only from the tips of the electrodes, which are then coated in platinum to
14
provide optimal neural reception. The array assembly is summarized in Figure 5.
Electrical Discharge Machine
(EDM) the array
Coat array with
gold strike
Solder array to flex-PCB
Remove electrodes
from base by EDM
Mount array
in substrate
-m1"m 010ir
Coat assembly with parylene
Solder connector
to flex-PCB
Create flexible Printed
Circuit Board (flex-PCB)
Create holes in polyimide
substrate and cut to size
P-M
Laser ablate the electrode tips
0
-10Coat electrode tips with platinum
6
Figure 5: Electrode array assembly steps (drawing by Bobby Dyer and Tim Fofonoff ).
Flexible PCB
The flexible printed circuit board (PCB) connecting the array to the electronics is
crucial not only for its obvious purpose of making the necessary connection, but because
it is part of the overall system design that makes TEAS superior to current research
equipment. Existing arrays use individual wires that must be painstakingly soldered onto
individual array electrodes, making the arrays costly to manufacture. With the flex PCB,
all traces are neatly packaged and the whole array can be mounted as a single component.
The current arrays have been mounted as through-hole components, with the backs of the
electrodes sticking through holes in the flex PCB on one side and getting soldered on the
other side. However, surface-mounting techniques similar to those used for chip-scale
electronic component packages are also being investigated by the electrode array
designers.
The wires connecting an electrode array to an external system must be very
flexible because a brain can move within a skull. Some of that movement is simply due
to the head moving around, but a large component of the motion comes from the whole
brain expanding and contracting with the animal's pulse. To make the PCB as flexible as
possible, the substrate was laser cut between traces. The traces were designed to be as
15
22.9 mm
I-
i
56.3 mm
Figure 6: Flexible printed circuit layout.
Figure 7: Flexible PCB detail around electrode array footprint.
small as possible while maintaining high manufacturing yield. The current version has
16
50 jm traces with 25 jim of the PCB substrate material on each side. A scale drawing of
the current flexible PCB is shown in Figure 6. Because the flex-PCB is only one-sided,
the trace routing is very tight, and the array footprint has various pad shapes to maximize
the soldering area for each electrode. A close-up view of the flexible PCB layout at the
array mounting point is shown in Figure 7.
Figure 8: Flexible PCB and 80-pin connector. The electrode array is soldered into the holes on the
left side of the PCB, which has laser cuts between traces to make it more flexible.
An important component of the flexible PCB module is a small, high-density
connector that will allow the flexible PCB to connect to the rigid PCB carrying most of
the electronics. A Molex7 connector pair8 (male part: 53794; female part: 54037) that is
only 1.15 mm high when connect is used. Unfortunately, the connector series is available
only in 60- and 80-pin versions. The lack of a 64-pin connector was common to many
17
manufacturers and connector lines, so the 80-pin Molex connectors represented the best
off-the-shelf solution. The connector and a completed flexible PCB are shown in Figure
8.
Electronics System
There are three main sections to the TEAS electronics: an analog front end that
does the necessary signal amplification and analog-to-digital conversion, a digital section
that performs peak detection and other processing, and a wireless communication module
(Figure 9)9.
This breakdown allowed simultaneous and independent design of the
different sections by different members of the design team. The interfaces between the
sections are dependent on the two sections they connect, but the digital system, which
connects to the other sections, is very flexible, allowing late modification to the interface.
Furthermore, the interface components of the analog and communications modules were
determined very early in the overall TEAS design.
4kx 16SRAM
64 RING BUFFERS
EIGHT
8-CHANNEL
2M x 8 SRAM
TRANSMIT FIFO
BUFFER
FPGA
16-BIT
MICROCONTROLLER
64 AMPLIFIERS
BLUETOOTH
Figure 9: Electronics system block diagram. The analog section consists of 64 amplifiers and 8
ADCs; the digital section, made up of an FPGA, two SRAMs, and a microcontroller, processes the
data from the ADCs and sends captured neural waveforms to the Bluetooth wireless interface.
Analog Electronics
The analog electronics is the interface between the brain and the rest of the
electronics.
The analog system provides the digital section with a simple, digital
18
interface that isolates the digital section from many of the difficulties of working in the
brain. Because the 64 inputs to the analog section are so weak, any form of multiplexing
prior to amplification isn't an option; therefore, the analog section contains 64 copies of
the same circuit. The size of the single amplifier circuit thus has a tremendous impact on
the overall size of the implant; the current analog design takes up approximately half of
the area taken up the entire electronics system. Power consumption considerations in the
individual amplifier circuits are also important because any increases in power
consumption are multiplied by a factor of 64.
The inputs to the analog section are the microvolt-level signals picked up by the
electrode array.
The peak-to-peak voltage on these signals is approximately 100
microvolts, requiring a gain of approximately five thousand to get to a 0.5 V peak-topeak voltage that is a minimum for the analog-to-digital converter.
The required
bandwidth, on the order of 10 kHz, puts the gain-bandwidth product at approximately 50
Mhz, well out of range of any low-power, single-stage amplifier. To simplify the power
system, we also decided on single-supply op-amps. Since the input signals can go both
positive and negative, a 1.5 V reference voltage is derived from the 3.0 V reference
voltage of the analog to digital converters. Figure 10 shows the final design for a single
channel of the analog circuit.
Besides amplifying the signal, the circuit also
3V
INPUT FROM
ELECTRODE
3V
+
.
-STAGE 1
G = 60
AIN
_
TO DIGITAL
3Va
FSUBSYSTEM
VREF
STAGE 2
G =70
3V
+
REFERENCE
ELECTRODE
1.5V
Figure 10: Single channel of analog amplifier.
performs RC high-pass filtering above approximately 200 Hz and low-pass, antialiasing
19
filtering below 15 kHz using the gain-bandwidth limitation of the op-amps. Two opamps are available in each package, so there are seven components per amplifier (five
resistors, one capacitor, and the op-amps). Even with this minimal circuit, the number of
components for the 64 amplifiers alone is 448 components.
Even with the smallest,
0201-size surface-mount components, which occupy approximately 1 mm x 1mm, the
analog circuitry consumes substantial space (approximately 30 mm x 30 mm for the
component footprints alone), and it is primarily for this reason that a more complex
amplifier and filter cannot be considered.
The 64 amplified signals are fed into eight separate 8-channel analog-to-digital
converters (ADCs). The ADCs thus provide multiplexing as well as the interface to the
digital section. For the implant to be useful, the Brown researchers required a minimum
of 12-bit sampling, and the 30 kHz minimum sampling requirement makes the minimum
aggregate sampling rate for each ADC 240 kHz. This sampling rate is low enough that
the ADC can be a very low power device, and the data rate is low enough to readily allow
a serial interface, which helps limit the package size of the ADC.
MAX1281"
Maxim's 10
was chosen because it meets all of the requirements in a small, TSSOP
package.
Bluetooth Wireless Communication Module
We determined early in the project that a commercial module using the new
Bluetooth protocol12 would be the most straightforward way of achieving the highbandwidth wireless connection we required. Bluetooth was designed for short-distance
wireless connectivity between small, low-power devices, and its spread-spectrum,
frequency hopping protocol was made to limit interference from ambient electromagnetic
noise. The data rate of 725 kbits per second (kbps) was acceptable but not outstanding,
especially compared to the 11 Mbps rates of wireless Ethernet cards. However, size and
power consumption were very high priorities; wireless Ethernet adapters are larger than
the entire space allotted to TEAS, and modules in packages other than those for plugging
into laptop PC card slots were not available.
The available Bluetooth modules were
effectively single components approximately the size of our other large components such
20
as the FPGA, and the Bluetooth module thus fit the TEAS approach of using commercial,
of-the-shelf parts.
The availability of Bluetooth modules in PC card format only
improved the attractiveness of Bluetooth as the wireless communication module because
less work would be necessary on the external interface: the Bluetooth card would
effectively be all the hardware required for the entire external interface, and all that we
would need to implement on the PC side would be software.
The prototype Bluetooth module is Cambridge Silicon Radio unit13 that is truly a
self-contained radio, unlike some alternatives that required external amplifiers or filters.
The 23 mm x 15 mm module has a standard asynchronous serial interface that provides
access to several layers of the protocol stack. One interface, HCI, allows the unit to be
controlled with relatively simple commands without detailed understanding of the
frequency-hopping algorithm. Most of the complexity is in setting up a connection; once
it is established, sending data is relatively straightforward. The only real problem is in
achieving the advertised bandwidth of 725 kbps: the highest data rate we have achieved is
approximately 500 kbps.
The TEAS analog electronics and wireless connection are
detailed by Johann Burgert.
Digital Electronics
The digital electronics system must read the analog-to-digital converters, process
the incoming data, and send the processed data to the Bluetooth module. The digital
section also contains the microcontroller, which governs the entire implant by controlling
the power supplies for the rest of the electronics. The front end of the digital electronics,
which must interface to eight serial ADCs simultaneously, is implemented on a field
programmable gate array (FPGA). The FPGA includes the circuitry for interfacing to a
small external SRAM that is used for peak detection. The FPGA also controls a large
SRAM to buffer data that the microcontroller will read and transmit to the Bluetooth
module. A block diagram of the digital electronics is shown in Figure 11. The digital
section is the focus of this document, and its design will be discussed thoroughly in
Chapter 3 of this thesis.
21
ADDR<11:0>
DATA<13:0>
EIGHT
8-CHANNEL
ADCs
---
SCLK
*
uCOD
uCADDR<7:0> 4
uCDATA<11:0>
BUFSIZE<2:0>
LOADBUFSIZE 4
SOUT<7:0>
SIN<7:0>
C
16-BIT
MICROCONTROLLER
*C
FPGA
OI
At
A
(P A
00
NEWDATA
OVERFLOW
RESULT< 7:0>
ACK
BLUETOOTH
_
LU
RESET
--
(9
16 MHz
CLOCK
4k x 16 SRAM
64 RING BUFFERS
CLK
<0
t
4*
2M x 8 SRAM
TRANSMIT FIFO
BUFFER
Figure 11: Digital electronics block diagram.
Power System
The power system consists of a rechargeable battery, the necessary accessories for
wirelessly charging that battery, and several voltage regulators that provide the correct
voltages to different parts of the electronics system. Most of the volume of the power
system, the battery and recharging circuit, can be implanted in the abdomen of a test
monkey, and the size of the system is therefore not a primary concern. The battery will
be a lithium-ion or lithium-polymer battery that has a nominal voltage of 3.6 volts. The
battery must have a capacity of approximately 13 kJ (1 amp-hour at 3.6 V), which will
allow for three hours of operation with the estimated 1 W power consumption of the
electronics.
To recharge the battery in a reasonable amount of time (overnight), the
charging circuit must deliver 100 mA. Work on this portion of TEAS has been very
limited, but preliminary designs have been able to charge the battery at 50 mA through a
22
10-mm separation.
Power management is critical to the design, and every component was chosen
with power consumption in mind. Table 1 gives a breakdown of the estimated power
consumption of the electronics, assuming 3.0 V operation. A lithium-ion or lithiumpolymer battery can readily provide the necessary current of 330 mA. There are four
separate voltage regulators on TEAS: one for the microcontroller, one for the rest of the
digital electronics, a third for the analog electronics, and a fourth for the Bluetooth
module. The microcontroller coordinates the functions of the electronics system, so it
must always be powered. The microcontroller can independently shut down the power to
the analog front end, the FPGA and SRAMs, and the wireless communication system.
The microcontroller can internally switch to an extremely low power mode that allows
the minimum average current consumption of the entire electronics system to be below 1
mA, which is necessary during charging and periods when the device is not in use. In
this low-power mode, the microcontroller can monitor charging status and occasionally
power up the communications system to check for any incoming commands.
Table 1: Power budget for TEAS electronics, assuming a 3.0 V power supply.
Analog Electronics
Amplifiers
ADCs
Total
Bluetooth Module
Digital Electronics
FPGA
2 MB SRAM
64 KB SRAM
Microcontroller
Clock
Total
Total for All Electronics
23
360 mW
60 mW
420 mW
180 mW
225
75
45
15
30
mW
mW
mW
mW
mW
390 mW
990 mW
3. Digital Electronics Design
The interface to the digital electronics section of TEAS was determined very early
in the project. The primary input to the system would be the data from eight 8-channel,
12-bit analog-to-digital converters (ADCs), and the system would process that data and
send any detected neural spikes to the Bluetooth module over an approximately 1 Mbps
serial link. The system would also have a secondary input in the form of a serial input
from the wireless link, over which any TEAS system commands would be received. As
with the rest of the project, the most important design constraints were size, power
consumption, and ready availability of components.
High-Level Design Choices
Given the requirements, there were two general design approaches that could have
been pursued. The system must read a very wide parallel input from eight ADCs, and it
must generate a completely serial output; the two main alternatives to dealing with the
parallel input were:
" using a high-speed microprocessor or digital signal processor and tackling the
problem in software;
" implementing custom parallel hardware.
The two options, and why we ultimately chose the parallel hardware approach, are
described next.
The High-Speed Processor Alternative
Using a high-speed processor was appealing since a single programmable device,
and thus a single development environment, would be necessary for the design. Also,
having greater available processing power in the implant might allow for more complex
triggering or better compression algorithms that would make better use of the limited
wireless transfer rate.
The main problem with the approach was that it was not
necessarily feasible, and even if it were, there might not be any time left after reading the
ADCs for the extra processing that made the approach attractive in the first place. The
24
requirement of sampling 64 channels at a minimum of 30 kHz makes the minimum
aggregate sampling rate 1.92 MHz.
Even with a processor such as a 200 MHz
StrongARM, a processor typical in high-end handheld computers, only 100 cycles per
sample would be available. A hundred cycles may initially seem more than adequate, but
the main problem is that, since the 64 channels are processed sequentially, the samples
from the individual channels are interlaced: after reading a sample, 63 other samples must
be processed before reaching the next sample for the first channel. A substantial portion
of the available processing time would thus be spent context switching. Even without the
context switching, a hundred cycles is not much time for analyzing a sequence of
samples, which would be necessary for advanced triggering or compression. To make
matters worse, the processor must also deal with the asynchronous communication with
the wireless module, whose small buffer must remain full to ensure optimal transfer rates,
and which may at arbitrary times receive new commands from the external user interface.
In addition to not having clear performance benefits, the single-processor option
wasn't clearly smaller or less power hungry than the parallel hardware approach. Highperformance processors typically do not have the level of system and peripheral
integration seen on smaller 8-and16-bit processors, which often have program memory,
data memory (SRAM), and hardware serial ports in one package. The high-performance
processor would thus not present a one-component solution to the digital system and
would instead require space comparable to that for the parallel-hardware approach chosen
for TEAS. The high processor speed and the need for additional components would also
make the power requirements similar to that of the alternative approach.
Besides the
consumption of the digital hardware alone, the high-speed system would also require
ADCs that are faster and therefore more power hungry.
A final disadvantage to the high-speed approach is that it would significantly
complicate the PCB layouts for prototypes and the final implant. Creating layouts for
high-speed digital electronics is not trivial even without consideration of how it might
interfere with the analog electronics or the wireless communication module. Because of
the lack of clear advantages to the high-speed approach and because of the added
complexity, we chose the parallel hardware alternative.
25
The Parallel Hardware Alternative
The parallel hardware approach, however, is not without its own issues. One of
the problems is that the required output of the digital system was ultimately not parallel,
and the data from the 64 channels need to be organized into a single serial stream
somewhere in the system.
Furthermore, interfacing to the Bluetooth module requires
complex protocols that are very difficult to implement as a straight hardware solution.
Therefore, a combination of programmable logic and a microcontroller is used for the
TEAS digital section. The downside to this design choice is that it required finding two
major components: the microcontroller and the programmable logic device (PLD).
It is worth noting that the conceptually different components of microcontroller
and PLD need not be physically distinct or in different packages. Many PLDs are large
enough to contain several large microprocessors, and pre-designed code for emulating a
processor in a PLD is readily available. More recently, devices that explicitly combine a
microcontroller with a PLD in one package have become available.
For example,
Atmel's15 Field Programmable System-Level Integrated Circuit (FPSLIC) 16 contains, in
one package, a 30,000-gate field programmable gate array (FPGA), an 8-bit Atmel AVR
microcontroller, and an SRAM bank accessible from both the FPGA and the
microcontroller. Unfortunately for TEAS, these single-chip solutions were more capable
than necessary for TEAS, and, as a result, they were too large and power hungry. The
multi-component approach has the advantage of allowing selection of components with
the minimal capabilities necessary to achieving the task at hand; different components
can also be completely powered down to minimize power consumption during idle or
recharging periods.
An important aspect to the microcontroller and PLD design was to break up the
tasks efficiently and to develop an interface between the two components.
This early
design decision was especially important since component selection is critical to the
success of the project, and large-scale changes might not be possible to implement once
components were chosen. Thus, the parallel-hardware approach, given that it could not
be implemented using just one component, was in some ways less flexible than the high26
speed controller approach. On the other hand, the parallel approach allows for more
independent implementation of subsections of the design, and thus allows a more
structured design approach that uses hierarchy and abstraction. For example, changing
the ADC interface protocol with the high-speed approach might cause timing changes
that would require significant rewriting of the processor code; with the parallel-hardware
approach, the change would be contained within a programmable logic unit that
interfaces to the ADC, and the microcontroller code wouldn't have to change at all.
The tradeoffs between the two approaches are dependent on the number of
channels that TEAS must record. Beyond 100 channels, the high-speed approach would
almost certainly have been impossible, but even a mid-range microprocessor could
readily have handled ten channels. With the 64 required channels, either approach could
probably have been implemented.
Ultimately, the parallel-hardware approach was
chosen for TEAS because it was more likely to result in a smaller, less power-hungry
design in a shorter amount of time.
Compression Considerations
The Bluetooth wireless connection is a huge bottleneck. Even with the theoretical
maximum bandwidth of 725 kbps, less than one thirtieth of the 2 million 12-bit samples
collected every second can be transmitted. By itself, buffering the data does not help
much because it piles up at the huge rate of almost 24 Mb per second. With the lack of
abundant memory in the implant and with a very slow connection to the outside world,
some form of compression prior to transmission is clearly necessary.
An important
design requirement from the Brown neuroscientists was that, should there be any
compression, it would have to be lossless, with the exception that they were only
interested in the neural spikes and their timing.
Indeed, triggering on neural spikes and sending only the spike information
provides a huge reduction in required bandwidth. Unfortunately, the compression factor
varies with the neural spiking rate, which can vary from 10 to 300 Hz. With individual
spikes lasting approximately 1.5 ms, the interesting data comprise 1.5% to 45% of all
collected data. If the average spiking rate were below 20 Hz, spike detection alone would
27
provide the thirty-fold compression necessary to compensate for the discrepancy between
the acquisition and transmission rates. Additional compression, however, would still be
desirable since only four channels spiking at a high rate would overwhelm the
electronics.
Given that the general shape of neural signals is known, it seems likely that that
knowledge could be used to effectively compress the spikes themselves. However, the
lossless compression requirement eliminated many substantial compression options.
Algorithms used for compressing electrocardiograph (EKG) readings, which have shapes
similar to neural signals, typically achieve 90% compression, but that compression comes
mostly from eliminating the uninteresting data between heartbeats, much like the spike
detection discussed above. Another major impediment to using knowledge about the
spikes' expected shape is the interlaced sampling of individual channels, which results in
samples for individual channels being scattered through memory.
It is not clear that any general-purpose compression approach would yield
appreciable benefits when applied to the interlaced signals. Even test runs of LempelZiv"
compression on non-interlaced spike samples (obtained from existing neural
recording systems) were unsuccessful. Given that the individual channel samples are
independent, interlaced samples of detected peaks are effectively random, making
lossless compression without first recovering the data structure almost impossible.
Achieving practical compression in real time would thus be challenging on a highperformance desktop computer, let alone on the limited microcontroller used in the TEAS
implant.
One last explored approach was delta-compression right in the front-end, parallel
hardware of the digital electronics.
This approach would require, for each channel,
additional storage for one sample that would always hold the previous sample value.
Then, instead of wirelessly sending the sample values, the differences would be sent-the
hope being that the range of changes would be much smaller than the range of values.
Unfortunately, some parts of the spikes have very steep slopes, and with the added
necessity of a sign bit to indicate the direction of the change, this simple scheme saved
only one or two bits per sample: in our tests, delta-compression required approximately
28
10 bits per sample. While the 17% compression would be nice to have, units of 10 bits
are difficult to work with because 10 is not a power of two. Since the digital electronics
components are all organized with 8- or 16-bit busses, taking advantage of the two saved
bits would require much more manipulation of the samples to pack them into 8- or 16-bit
chunks. Combined with the added hardware requirements to do the subtraction on-thefly, the added complexity was not worth the potential payoff.
Thus, it was determined that the nature of our data did not allow for simple
compression and there was insufficient processing power on the implant to do more
complicated compression in real time. Thus, TEAS relies on a relatively low average
spiking rate on the sampled electrodes to keep the transmit buffer from overflowing. To
lower the negative impact of the low-spiking-rate requirement, the user interface will
allow the researcher to turn off any channels that correspond to inactive electrodes or that
are otherwise uninteresting. The number of samples per spike can also be varied, up to
the extreme where only the time for each spike is sent; in that mode, the available
bandwidth can support all 64 channels spiking at 300 Hz.
Breaking Up the Digital Section
Given the design decisions to implement a parallel-hardware approach and to
limit compression to straight neural spike detection, the next task was to determine how
the digital section should be broken up between the programmable logic device and the
microcontroller.
Provided that a good division into separate sections could be
determined, those sections could then be implemented almost independently. Component
selection would be closely tied to this choice because of the general TEAS design
approach of rapid development using readily available components. Once components
were selected, it would be costly and time consuming to change the section divisions in a
way that exceeded what was achievable within the flexibility of the chosen components.
The programmable logic section clearly had to take care of the ADC interface.
Spike detection and pre-trigger buffering was also appropriate for the high-speed logic
since a lot of data had to be pushed around quickly. The microcontroller, on the other
hand, was selected primarily for dealing with the Bluetooth module and higher-level
29
control of the entire implant.
It became clear from these task assignments that the
following section separation was appropriate: the programmable logic would do all
incoming data processing and asynchronously present the microcontroller only with data
to be transmitted over the wireless link; and the microcontroller would, at its own
discretion, arbitrarily read data from the programmable logic section and write to the
High-level communication protocol
implemented in microcontroller to
send data to external system
Microcontroller
Asynchronously accessible
digital representation of
neural spikes in original input
Programmable
Digital Logic
Performs peak detection
to pick out relevant data
Clean, digital representation
of original input
Analog Electronics
Weak signals are amplified
and digitized
Analog
Input
Electrodes are like antennas
that pick up very weak signals
Electrode Array
Figure 12: Abstraction and hierarchy in the TEAS electronics design.
Bluetooth module. Except for some initial setting up of thresholds and other parameters,
this arrangement allows the microcontroller to be oblivious to the details of the data being
collected: to the microcontroller, the programmable logic section is just a black box from
which data can be read at any time, indistinguishable from any other parallel data source
such as FIFO. The microcontroller must then implement a high-level protocol to get the
data to the external logging system without any errors. The hierarchy and abstraction for
30
the entire TEAS electronics design is shown in Figure 12.
Information (neglecting
handshaking signals) flows in only one direction, and each level insulates the next level
from many of the details of the signals the brain implant is recording.
31
The Programmable Logic System
The general breakdown described above makes the programmable logic system
the heart of the data acquisition system within the implant. As its input, the system has
eight analog-to-digital converters that it must also control. The output is a FIFO buffer
that can be read at any time by the microcontroller, which is generally oblivious to the
contents of the data and just deals with getting them, uncorrupted, to the external system;
the format of the data can therefore be determined by the programmable logic system.
The output buffer of the programmable logic section also serves as a secondary transmit
buffer since the microcontroller and Bluetooth module have very limited buffers. Since
the microcontroller reads data from the programmable logic unit only when the Bluetooth
module can take more, this output buffer must be as large as possible to prevent bursts of
neural activity from overwhelming the system. Of course, the programmable logic must
also perform its central role of carrying out peak detection and time-stamping on the
incoming data. There are thus four main sections to the programmable logic system: the
ADC interface, the triggering or spike detection system, the transmit buffer controller,
and global counter. These sections are examined in detail after a description of the
components used to implement the design.
Choosing Components, Part 1: Programmable Logic Device Selection
Choosing the programmable logic device for TEAS was something of a chickenand-egg problem: it was difficult to select a device without first knowing more about
what would be put on it, but those very details of the design were not necessarily
independent of the device that was chosen. Many devices had special features that might
have been useful, but the potential usefulness could not really be evaluated without
designing a substantial portion of the system around those features.
One feature that
would have been especially useful was integrated SRAM, which could have been used
for individual channel buffers used for recording peaks; however, the smaller devices that
were candidates for TEAS did not have sufficient memory.
Special features were
ultimately ignored because they were difficult to evaluate, and because using them would
require specialized development environments.
32
Even comparing general sizes or
densities was difficult because each manufacturer, and even different product lines from
the same manufacturer, had different measures of features and performance. Complex
programmable logic devices (CPLDs) are typically measured in terms of number of
macrocells, whereas the main parameter with field-programmable gate arrays (FPGAs) is
usually the number of programmable gates.
To make a better-informed decision, a general design was made in VHDL
(VHSIC (Very High Speed Integrated Circuit) Hardware Description Language); the
design itself is described below. The preliminary design effectively eliminated CPLDs
because of their limited size.
The CoolRunner series of CPLDs from Xilinx18 had
seemed particularly attractive, and a version with 512 macrocells might have been large
enough for the design; unfortunately, that version was not expected to be available for
many months. The Delta39K series from Cypress" promised CPLDs at FPGA densities,
but they were also just in development. Other CPLD lines typically do not have more
than 256 macrocells.
The lack of sufficiently large CPLDs was unfortunate because
SRAM-based FPGAs need to be configured every time they are turned on, requiring an
additional component that stores the configuration file in a non-volatile format.
With FPGA densities being much higher than those of CPLDs, the primary
parameters to look for became small physical size and low power consumption. Given
that the device would require over 100 1/0 lines, the some form of BGA (ball grid array)
packaging was essential. Power consumption was very difficult to judge because it is
very dependent on the particular configuration of the device. Ultimately, the Flex 1 0k30A
device from Altera2 0 was chosen for TEAS. The FlexlOk3OA 2 was available in a 1-mmpitch BGA package that was just 17 mm on a side (see Figure 13), had 30,000 usable
gates, had the lowest claimed power consumption, and, perhaps most importantly, was
immediately available. Once the FlexlOk3OA was chosen, the design was refined around
that part. The device is available in several different speed grades, but speed wasn't too
much of an issue because the design requires clock speeds under 20 MHz, which is
extremely slow for FPGAs.
33
Figure 13: The FPGA is one of the largest components in the design.
Choosing Components, Part 2: Transmit Buffer SRAM and Ring Buffer SRAM
Due to the huge difference between the possible data acquisition rate and the
maximum wireless transfer rate, obtaining a very large memory component for the
transmit buffer was crucial to achieving high performance in TEAS. Unfortunately for
the small development team with a very low expected production volume of TEAS units,
competing with large cell phone and handheld computer manufacturers, who also wanted
small, high-density memories, was very difficult. Many manufacturers would not speak
to a potential customer unless he was interested in at least thousands of units, and the
newest, smallest, highest-density devices were not available through distributors that
2
were willing to deal with small quantities, such as Digi-Key1 . Also, single-chip SRAMs
typically go up to about 8 Mbits in size, which is only enough for approximately 150
spikes per channel. While this number of spikes is acceptable, the buffer could
potentially fill up in a matter of seconds. A larger SRAM would hold more spikes, which
would make the buffer more effective because fluctuations in neural firing rates occur at
time scales close to those during which a smaller buffer could overflow. Fortunately,
24
Toshiba" provided sample units of a new 16-Mbit SRAM, the TC55W1600FT , which
has very low power consumption and comes in a TSOP48 package that measures 20 mm
x 12 mm. The SRAM is one of the largest components on TEAS, but it is crucial to
34
smooth operation during periods of higher neural spiking, which is usually especially
interesting. The TC55W1600FT was also particularly appealing because the memory can
be accessed as IM x 16 or 2M x 8, which allowed commitments to bus widths to be
made later.
Besides the large buffer SRAM, a smaller SRAM would be necessary to
temporarily hold data samples prior to triggering. The SRAM needed to have a bus width
of at least 12-bits to allow rapid sample transfer without shuffling around individual bits
separately from each other; since 12-bit bus widths aren't typical, a 16-bit device was
necessary. Such devices are abundant, so availability, power consumption, and package
size were used to choose the Cypress CY62126BV2 5 , which comes in a 48-ball BGA that
measures just 7 mm x 7 mm. Since it is very difficult to work with BGA packages,
another SRAM with the same interface but in a TSOP32 package was used for
prototyping. Ultimately, however, finding and using the smallest available packages is
crucial to achieving the required TEAS size.
ADC Interface
The analog section uses eight Maxim MAX1281 single-supply, low-power, 8channel, 12-bit, serial ADCs. The serial interface is used both for reading samples and
for setting ADC parameters such as channel selection and power mode. The MAX1281
uses Serial Peripheral Interface (SPI), a synchronous serial protocol supported by many
8-bit microcontrollers. The digital section front end must serve as the SPI "master" for
all eight ADCs by generating the serial clocks and initiating conversions.
The main points of the MAX1281 interface are shown in Figure 14, which shows
how the ADC would be used with a microcontroller that has SPI support. First, the
controller must send an 8-bit control word, which specifies parameters such as the
channel to be sampled. The first bit of the control byte must always be set, and it initiates
a conversion. After the control byte is sent, two bytes are read back. The two bytes
contain the 12-bit result, padded with one leading zero and three trailing zeros. A single
conversion therefore takes 24 serial clock cycles. The data for both input and output lines
are always valid on the rising edge of the serial clock.
35
12
8
14
16
24
20
SCLK
DOUT
DIN
A2 AlIA0 u
PD1 PDOI
MSB
D D101 D91 D8 D7 D6 D5 D4 D31 D21 D
START
S
Control Byte
LSB
DOI
o
ADC Result
A2:AO - channel selection
UNI/BIP - 1 = unipolar, 0 = bipolar
SGL/DIF - 1 = single ended, 0 = differential
PD1,PDO - power mode select
Figure 14: ADC interface timing diagram for reading one sample.
The interface can be run more quickly when the input and output transactions are
not constrained to 8-bit units, as shown in Figure 15. A control byte can be sent every 16
clock cycles, provided that the conversion result can be picked out at the correct time,
which is very simple with the programmable logic used in TEAS. The overlap of input
and output operations allows a much faster sampling rate, and the overlap is necessary to
achieve the 30 kHz minimum sampling rate required of the TEAS system.
1
24
16
8
32
SCLK
DOUT
DIN
S CONTROL BYTE 1
S CONTROL BYTE 0
I
CONVERSION RESULT 0
CONVERSION RESULT 1
*
Figure 15: ADC interface timing for reading a sample every 16 clock cycles.
Since there are no constraints on the timing of parallel conversions among the
eight ADCs, the control byte and serial clock can be the same for all eight 8 ADCs.
Therefore, the initial ADC interface design, shown in Figure 16, had a single output shift
register, the output of which would connect to all eight ADCs. All eight results would
therefore also appear simultaneously on eight separate result lines. Each ADC control
channel on the FPGA had a corresponding input unit consisting of a receive shift register
36
and a receive buffer. A properly timed "load" signal would transfer the contents of the
shift registers to the buffers, providing the next stage of the digital system with eight
buffers that always contained the most recent samples from the eight ADCs.
To
SCLK
JI
-
--
sclk
4
ADCOAD7channel
-
-
---
- -
I1
Se
power
power:,
down
3
To DIN
on
ADCOADC7
channel
.3
SEL2:0 0111
init
init
8
Transmit Shift Register
shift
shift
-- -.-..............
ADCO DOUT
P,
:Serial I
In
LSB
Receive Shift Register
shift
i i i
MSB
12
load:
Receive Buffer
2
AD]O
A DC I
ADC2
ADC3
ADC4
ADC5
ADC6
D OU T
DOUT-Al
O
DOUT
DOUT
DOUT DOUT-
ADC7 DOUT
- -... -........
-................
ADC result ,
AORESULT
lR S L
RESULT
-........ ......
A2
A3
A4
A5
9
........................
A 6...R
E...U LT.
A6
RESULT
Receive Shift Register
Serial
In
-
.......... ...
.....
...........
LSB
12
Receive Buffer
12
RESULT
RESULT
RESULT
RESULT
12
shift:
MSB
load
ADC resultA7
..
..
..
..
..
...
....
..
..
..
...
..
...
..
..
..
..
...
..
.....
....
..
..---1
iP
U
2
A7 RESULT
Figure 16: Initial, highly parallel ADC interface block diagram.
The original design described above adheres strictly to the parallel-hardware
approach of the digital section: the hardware for all eight ADCs is a set of exact replicas
that take eight parallel inputs and provides eight parallel outputs that can be used
37
downstream by additional parallel hardware. However, later refinements to the next
stage of the digital system, the triggering system, made simultaneous availability of all
eight ADC results unnecessary. As described in the overview of the digital system, the
output of the digital section must be sequential, so the change from parallel to serial must
happen somewhere within the digital section. Implementing parallel versions of small
digital modules such as the input shift registers is simple, but achieving parallel memory
access is much more difficult. Given that the triggering system (described in the next
section) uses an external SRAM to store ADC results, implementing truly parallel
memory access would require multiple external SRAM components along with many
parallel address and data busses. The size and power restrictions on TEAS make multiple
SRAMs unattractive, if not unfeasible, so some form of multiplexing of a single SRAM is
required. Given that ADC samples are stored in a single SRAM sequentially, it becomes
unnecessary for all eight ADC samples to be available simultaneously and at all times.
The above conclusion was used to make the current ADC interface a more
efficient, more tightly integrated part of the digital system. Instead of sending the control
byte simultaneously to all eight ADCs, the output section sends eight different versions of
the control byte, each staggered by two clock cycles; the starting times of the ADCs are
thus evenly distributed throughout the 16-cycle sample period.
The results are then
received every two cycles, and instead of using a receive buffer on every input channel, a
multiplexer selects the shift register that currently holds a valid result. The multiplexed
result can then be buffered if it is needed for both cycles or used directly if the triggering
system only needs the result at the beginning of the time it has allotted to each channel.
Some attention must be paid to the details of the interface to synchronize the current
multiplexer result with the rest of the system. The lower bits of a global counter are used
to indicate the current channel being processed, and the ADC interface must make the
correct result available at the correct time. Because of the delay between starting a
conversion and getting the result, the serial output section must add one to the channel
number requested for the result to match the global counter. (This addition of one is not
strictly necessary since the electrode numbers could just be relabeled; however, a 3-bit
increment is very minimal, and it reduces the possibility of confusion in the electrode-to38
channel-number mapping, which is already complicated by PCB layout issues.)
GLOBALCOUNTER8:1
CHANNEL
1
3
1
SEL2:0 1 1 1 1
I
I
I
I
I
I
I. .
I
I
I I
I
load
8
23-bit Transmit Shift Register
I
sh ift
I I I I
I I I I
DOUT7
DOUT6
DOUT5
DOUT4I
DOUT3
DOUT2
DOUTO
DOUTO
SCLK 4
-
1
Receive Shift Register
1
11
Ishift
0
SEL
/
12
ADC2 DOUT
12
ADC3 DOUT
12
ADC4 DOUT
I
/
12
ADC5 DOUT
ADC6 DOUT
3
MSB
0
LSB
ADCI DOUT
/
41
. ..
..
12
'
'12
ADC7 DOUT
12
ADC8 DOUT
S12
Figure 17: Final ADC interface block diagram.
39
parallel
result for
current
12 12channel
The final version of the ADC interface is shown in Figure 17. The elimination of
the input buffers in the original, more parallel version is significant because the eight
buffers required 108 flip-flops. The new version does require more transmit hardware,
but the size of the ADC interface as a whole is almost halved. A reduction in size is
almost always useful since it reduces constraints when fitting the design onto the FPGA.
Although the ADC results are presented sequentially, the interface to the rest of the
digital system is very clean: the ADC module reads the global counter, and always
outputs the ADC result for the channel specified by the counter. The ADC interface thus
puts some additional constraints on the rest of the system by eliminating the possibility of
any additional parallel hardware, but a sequential approach to the rest of the system is
both required by the external SRAM and likely to lead to a more compact overall design.
The interface assumes a serial clock speed of 4 MHz, which results in an aggregate
sampling rate of 2 MHz and an individual channel sampling rate of 31.25 kHz. The serial
clock can potentially be increased up to 4.8 MHz (37.5 kHz per channel), which is the
upper limit for the MAX1281. The VHDL source code for the ADC interface is listed in
Appendix A3 and Appendix A4.
Spike Detection System
The output of the ADC interface is read by the spike detection unit, which is the
central component of the TEAS data acquisition system since it determines which data
are saved and transmitted outside of the implant. Because data samples are stored in a
single external SRAM, the triggering system processes each channel sequentially,
requiring this processing to execute very quickly. Fortunately, the triggering mechanism
can be as simple as a comparator that checks to see if the incoming data values exceed a
predetermined threshold. However, the spike detection system is more complicated than
the trigger mechanism alone because it must keep track of additional state. A spike is
detected only after the spike is well under way, so all samples must temporarily be saved
even without a channel having triggered. After triggering, the relevant saved samples
must be sent to the large transmit buffer, but this relatively simple-sounding task is
complicated once again by the lack of processing time, which requires most tasks to be
40
broken up.
The spike detection system is thus perpetually switching contexts, and
designing an effective method of quickly saving and retrieving the state of individual
channels was critical.
Depicted in figure 18 is the expected data waveform of a neural spike, along with
some of the terms that are used in the description of the spike detection system. A spike
is detected, and a channel triggers, when a sample exceeds the channel's threshold value.
A certain number of samples are pre-storedbefore triggering, and additional samples are
post-stored after triggering. Because of limited processing time, stored samples are read
out only after all pre-store and post-store samples have been recorded. The total number
of samples per spike is set for all channels simultaneously, but the thresholds and number
of post-store samples can be set independently for each channel, allowing detected spikes
to be properly framed around the trigger point. For example, with the total number of
samples per spikes set to the maximum of 60, setting the post-store parameter to 40
would result in capturing 20 data samples before the threshold is exceeded and 40
samples after the trigger point.
THRESHOLD
POSTSTORE
PRESTORE
Figure 18: Prestore, threshold, and poststore on a typical neural spike waveform.
To execute effectively the continual context switching resulting from changing
from channel to channel, the external SRAM is organized as shown in Figure 19. Each
channel is allocated 64 locations, of which the first is a status variable that holds the
current state of the corresponding channel.
41
The next three locations hold other
parameters for the channel, such as the triggering threshold and the number of post-store
samples to record. The fourth location is currently unused, but it could be used for an
additional parameter such as an "un-trigger value" that must be crossed after triggering
before a channel can trigger again. The SRAM has a 16-bit data bus, but only 14 bits are
currently required because of the width of the status variable. Since the samples have 12
bits, this leaves two bits available for possible marking of samples, although this is not
done in the current design. Should the system need to be expanded, two additional bits
are readily available by using all 16 bits of the SRAM. Because there are 64 channels
that are each allocated 64 locations, a total of 4k words are necessary.
4Kx1 6 Sampling Unit Memory Organization
0x40
Ox0000
CHANNEL 0
STATUS
CHANNEL 1
THRESHOLD
*8
POSTSTORE
0x4]
0x0040
0x42
0x0080
0x43
UNTRIGGER
OxOFCO
CHANNEL 63
04
6 A44
60-SAMPLE
RING BUFFER
OxOFFF
Ox7F
Figure 19: Spike detection system SRAM organization.
The 14 bits of the status variable must hold all information necessary to determine
the state of a current channel. Although there are conceptually only a handful of different
states in which a channel can be, 14 bits are required because each channel accesses its
memory independently. The data analyzed on each channel are effectively independent,
and one channel might be recording pre-store samples while another channel might have
already triggered and be reading out previously recorded samples. As shown in Figure
42
STATUS
5:0 - 6-bit counter
11:6 - 6-bit address
13:12 - status
14 - unused
15 - unused
Figure 20: STATUS variable bit descriptions.
20, six bits of the status variable, bits 6 through 11, indicate the next address to be
accessed. Another six bits are used to keep track of how many post-store samples have
been stored, and the remaining two bits indicate the more general state of the channel,
which can be one of the following:
" PRESTORE. In this state, the channel has not triggered; therefore, a sample
should be stored and compared to the threshold. If the threshold is exceeded, the
channel will be in the post-store state next time it is processed.
*
POSTSTORE. In this state, the channel has triggered, but all post-store samples
have not yet been collected. A sample is stored, and the 6-bit counter in the status
memory location is used to keep track of how many more samples must be stored.
After the correct number of samples has been recorded, the channel will go into
the channel information state.
*
CHANINFO. In this state, the channel number and a time stamp are sent from
the spike detection system to the transmit buffer. The next state will be the data
reading state.
" READ. In this state, samples that have been stored are read and sent out to the
transmit buffer. The status variable's 6-bit counter is used to read the correct
number of samples. After the buffer is emptied, the channel goes back to the
43
PRESTORE state.
Of the 64 memory locations allocated to each channel, 60 are available for storing
samples.
These 60 words are organized as a ring buffer, in which a pointer always
indicates the next location to be accessed.
After writing a sample, the pointer is
incremented, and it overflows from address 63 to address 4. Thus, the 60 most recent
samples are always in memory, and the pointer always points to the oldest sample, which
gets overwritten with the newest sample. When the post-store samples are all recorded,
the pointer already points to the first data location to be read (since it is oldest), and
reading the memory in order from that point will return all of the 60 data samples in
order. The size of the ring buffer can readily be modified by changing the point to which
the pointer overflows; for example, if it overflows from 63 to 60, the buffer effectively
contains only four elements. Changing the buffer size and recording fewer samples per
channel allows for more effective use of the limited wireless link, which is the reason for
having a spike detection system that transmits only the interesting data. With a sampling
rate of 31.25 kHz, 60 samples will store 1.92 ms of a waveform, but with typical neural
spikes lasting only 1 ms, only 32 samples might be necessary. The flexibility of the spike
detection system and its ring buffers could therefore potentially almost double the rate at
which spike information can be transmitted over the wireless interface.
The timing of SRAM accesses and the time available for processing each sample
can be selected by the clock frequency of the FPGA. The ADC interface presents new
samples at a 2 MHz rate, which is required to meet the individual channel sampling rate
minimum of 30 kHz. The faster the FPGA clock rate, the more can be accomplished in
the 500 ns available for processing each sample, but a higher clock rate will also result in
higher power consumption in both the FPGA and the SRAM. Choosing a low SRAM
access speed also allows low-speed, low-power SRAMs to be used.
Because power
consumption is such a large concern, a clock speed of only 8 MHz is used. With an 8MHz clock and its 125 ns period, 70 ns SRAMs can be used safely without having to pay
excessive attention to the details of the SRAM interface timing. The given clock speed
allows for four processing cycles per data sample; of those four cycles, two must be used
44
in reading and writing the status variable. All other operations, such as reading and
writing samples, must occur in two cycles.
The two-cycle limit makes it almost impossible to simultaneously store and
retrieve data samples in one 500-ns data sample period. Before triggering, the threshold
value must be read, leaving only one cycle, which must be used for storing a sample.
Fortunately, the nature of the neural spikes being acquired allows breaks in data
acquisition immediately after spikes occur: the highest expected spiking rate is 300 Hz,
which corresponds to a 3.3-ms period over twice as long as the 1.5-ms length of a spike.
Therefore, TEAS does not sample channels immediately after the post-store samples are
recorded, when the data values are transferred from the ring buffer SRAM to the transmit
buffer SRAM. To minimize the time that a channel is not capable of triggering, two
samples are read out in the two cycles available when processing a channel; a channel is
thus temporarily off for half as long as the spike sampling period. For example, with the
capture time set to the maximum of 1.92 ins, corresponding to 60 samples, a channel
would effectively be off for approximately 1 ins. The exact time that a channel is off is
slightly more than half of the capture period because the channel number and a timestamp
must be transferred to the transmit buffer.
A state diagram corresponding to the ring buffer control system's actual VHDL
implementation, listed in Appendix Al, is shown in Figure 21. The actual states closely
match the four conceptual states listed earlier, with each sequence from the readSTATUS
to writeSTATUS states corresponding to one of the conceptual states.
For example,
when a channel is in the state earlier called PRESTORE, it goes through the following
sequence of states in the four clock cycles allocated for each sample: readSTATUS,
readTHRESH, writeSample, writeSTATUS. The only channel general state that does not
correspond to a single, 4-cycle path through the Figure 21 state diagram is the
CHANINFO state, when information about the channel is placed in the transmit buffer.
The channel number and time stamp are transferred in two separate sample processing
periods because the four available cycles are not sufficient for recording both the channel
number and the time stamp. Only 6 of the 24 available bits for channel designation are
necessary; the 18 leading bits are set to zero to indicate that a channel has triggered and
45
that samples for that channel will now be interspersed within the transmit buffer (the
details of the data organization in the transmit buffer are discussed in the following
section). To make sure that the 18 zeros are a unique identifier, any data samples that
have a value of zero, which should be very unlikely, are incremented by one.
readTHRESH
readSTATUS
Cycle 1
readPOSTSTORE
writeSample
getChan1I
getChan2
getTimel
getTime2
readlI
read2
Cycle 2
Cycle 3
writeSTATUS
Cycle 4
500-ns Sample Processing Period
Figure 21: Spike detection system state diagram.
The spike detection system takes in all samples, and using only four clock cycles
per sample, outputs only relevant data in pairs of 12-bit words. The design allows for a
minimal clock speed while providing a reasonably flexible triggering mechanism. The
design is also flexible in the sense that some of the details of the triggering method or
46
other data processing can be modified without requiring extensive redesigning of the
spike detection system. The output data are read by the next system, the transmit buffer
control, which provides an interface between the spike detection system and the
microcontroller.
Transmit Buffer Control
The transmit buffer is a large, 16-Mbit SRAM that holds data that are ready to be
transmitted over the wireless link. The transmit buffer control system makes the SRAM
look like a FIFO buffer to the spike detection system and the microcontroller.
The
transmit buffer controller serves as the interface between the highly synchronized spike
detection system, which can output data at any time, and the microcontroller, which
asynchronously requests new data any time the wireless link is free.
The Toshiba TC55W1600FT 16-Mbit SRAM can be accessed either as 2M x 8 or
IM x 16. The 2M x 8 organization was chosen because the SRAM must be used as
efficiently as possible, and packing pairs of 12-bit words into 8-bit chunks is easier than
packing them into 16-bit chunks. Also, the 8-bit organization requires fewer I/O lines
and PCB traces, which could simplify routing. A final reason for the 8-bit organization is
that the microcontroller reads data eight bits at a time, so having an 8-bit mindset to the
transmit buffer control should result in a more unified design.
Because the SRAM itself is not a dual-port device, the transmit buffer control
requires its own small output buffer from which the microcontroller can read at any time.
The input portion of the transmit buffer control is synchronized with the global clock so
that the arrival of samples from the spike detection unit can be predicted and scheduled
efficiently.
Ideally, to simplify synchronization and to limit power consumption, the
buffer control would run at the same 8 MHz clock speed as the spike detection unit. The
transmit buffer control system achieves this goal by synchronizing its SRAM accesses
with the spike detections system as shown in Figure 22. The transmit buffer control is
aligned with the four-cycle, 500-ns sample processing period of the spike detection
system. If the spike detection system outputs any data, they appear in cycles 2 and 3.
Because of the 8-bit access of the 16 Mbit SRAM, three write operations, taking up three
47
cycles, are necessary to record all 24 bits of the two samples. In the remaining clock
cycle, the transmit buffer control can read the SRAM to update its small microcontroller
interface buffer. The timing of reads and writes between the two SRAMs is shown in
Figure 22.
2Mx8 Transmit
4Kxl 6 Ring Buffer
read byte
1 Load STATUS
2
2
YES
reading?
NO
Load
write byte 1
read sample
two 12-bit
samples
converted to
3
write sample
read sample
write STATUS
write STATUS
----- - -- -- - write byte 2
3
4
4
write byte 3
Figure 22: Timing of data transfer between spike detection and transmit buffer SRAMs.
The imbalance between the three writes and the one read in the transmit SRAM
reflects the discrepancy between the data acquisition and wireless transfer rates.
However, the situation is not as bleak as it may seem because the three writes do not
necessarily happen every cycle. Even with each channel triggering constantly, the spike
detection system produces samples only one third of the time. On the other hand, the
SRAM read also does not happen every cycle because the wireless link cannot support
sending a byte every 500 ns.
The transmit SRAM is accessed as a single large ring buffer, with one pointer
holding the next write location and another pointer holding the next read location. If the
read pointer catches up to the write pointer, the buffer is empty, whereas if the write
48
pointer catches up to the read pointer, the buffer overflows. These two conditions are
relayed to the microcontroller via two status lines so that the microcontroller knows when
to read data from the buffer and when it has filled up. The transmit buffer control always
presents the latest byte to the microcontroller on a parallel bus; the microcontroller
acknowledges that it has read the data by toggling an acknowledge line, which causes the
SRAM read pointer to be incremented. The transmit buffer control VHDL code is listed
in Appendix A2.
Unifying the Programmable Logic Modules: the Global Counter
The global counter synchronizes the other three systems running on the FPGA:
the ADC interface module, the spike detection system, and the transmit buffer control.
The upper 24 bits of the counter serve as the time base for time-stamping detected neural
spikes. 9 bits are used to synchronize the lower FPGA components, making the global
counter size 33 bits. The interpretations of the various bits of the global counter are
summarized in Figure 23; note that some bits have several meanings since they are
accessed by multiple modules.
32
9
0
Timestamp Counter (24 BITS)
8
0
I
Channel Number
I
I
5
I
2
ADC Control Counter
SRAM Access Clock (8 MHz)
ADC Serial Clock (4 MHz)
ADC Channel Number
Ring Buffer State Machine
Counter
Figure 23: The 33-bit global counter.
Although the fastest clock used by the internal modules is only 8 MHz, accessing
SRAM once per cycle requires changing the interface signals on both rising and falling
clock edges, and a square clock (50% duty cycle) is necessary to guarantee that all of the
SRAM timing requirements are met. Thus, the FPGA runs off of a 16 MHz oscillator
49
that is divided to a square 8 MHz clock in the global counter. The 8 MHz clock is also
output to an 1/0 line connected to the microcontroller's clock input, allowing the
microcontroller to run at its maximum speed without requiring another oscillator.
The global counter VHDL file is included in Appendix A5; all VHDL modules
are brought together in Appendix A6, teas.vhd.
50
The Microcontroller
As
described
at the
beginning
of the digital
electronics
section, the
microcontroller deals primarily with interfacing to the Bluetooth module and higher-level
control of the entire implant.
Because the FPGA deals with high-speed, low-level
hardware issues such as controlling the ADC, the microcontroller has to be just powerful
enough so as to not be a bottleneck in the flow of data from the transmit buffer to the
Bluetooth module. A hardware universal asynchronous receiver and transmitter (UART)
is desirable but not absolutely necessary since a UART could be implemented externally,
in the FPGA. Other peripheral features typically available on small microcontrollers,
such as ADCs and pulse width modulation output modules, are not necessary, but
FLASH program memory and the ability to self-reprogram are important to keep the
digital system flexible and modifiable, even after implantation.
As with the other
components in TEAS, size and power consumption are the other crucial parameters.
Several popular 8-bit microcontrollers, such as Microchip's
26
PIC series and
Atmel's AVR series, were evaluated for use in the TEAS system, but with maximum
performances of approximately 5 MIPS, the 8-bit units were too slow. Some PIC clones
that run at over 50 MHz were fast enough but too power hungry. Other processors were
too large, too small, required higher voltages (over 3.6 V), or didn't have enough
memory.
In the end, a new 16-bit microcontroller from Texas Instruments 27 , the
MSP430F14928,29, was selected. Although the top speed of the chip is only 8 MHz, it has
a very flexible UART that allows for high baud rates that aren't restricted to straight
divisions of the primary clock.
Aside from possible performance limitations, the
MSP430F149 has features perfectly suited to TEAS:
0
Extremely low power consumption. The MSP30F149 can run at down to 1.8 V,
with current consumption in the few tens of microamps, while operating. As with
other microcontrollers, a sleep option reduces the minimum current consumption
further.
0
60 kB of FLASH. 60 kB of internal memory is among the largest among small
microcontrollers.
The device can also reprogram itself.
The large program
memory turned out to be very useful since it is used to store the FPGA
51
configuration file (discussed in detail below).
*
Flexible clock. The MSP430F149 is unique in its ability to change clock sources
and operating speeds while running. Because of this feature, the TEAS digital
section requires only one clock source, which is used by both the FPGA and the
microcontroller.
*
Small package.
The microcontroller has 48 I/O lines in a compact, TQFP
package that is only 12 mm on a side.
Because the microcontroller is the interface between the digital section and the
Bluetooth module,
different
people worked
on code
for the microcontroller
simultaneously. The microcontroller code for the different tasks it must perform has not
yet been integrated, and details of the interfaces between the microcontroller and other
components have not been fixed. Within the digital section, one of the most crucial tasks
for the microcontroller is configuring the FPGA and then switching to a clock provided
by the FPGA.
After this initial power-up sequence, the microcontroller becomes
available to execute other code to run the implant. The lack of overlapping between
different microcontroller tasks should keep integration of all microcontroller code
relatively simple.
FPGA Configuration
One of the drawbacks to the SRAM-based FPGA is that it loses its configuration
whenever it loses power. Typically, FPGA-based designs use a separate memory device
that runs at power-up to configure the SRAM. Because of the severe size constraints in
TEAS, adding an additional component to the digital system was very undesirable.
Therefore, a novel scheme based on the microcontroller is used to avoid additional parts.
The relevant connections between the FPGA and microcontroller are shown in
Figure 24. The FPGA is configured using the PS (passive serial) scheme to limit the
number of I/O lines used on the microcontroller. As shown in Figure 25, configuration is
initiated when the microcontroller pulses nCONFIG low. The FPGA pulses nSTATUS
low in response, after which the microcontroller sends the configuration file serially, least
52
significant bit first.
The microcontroller must also provide the serial clock.
Once
configured, the FPGA stops pulling the CONFDONE line low, after which at least ten
more serial clock cycles are necessary to complete the setup. Should there be any errors
during configuration, the FPGA pulls down the nSTATUS line.
VCC
MSP430F149
MICROCONTROLLER
VCC
VCC
EPF10K30AFC256
FGPA
1k
R-S
P1.6
P1.5
P1.7
P5.5
P5.6
18
C15
CS
A15
C2
1711
19
CONFDONE
C14
STATUS
N4 N CONFIG
49
B2
50
Al
TDI
TMS
DEV OE
DEV CLR
DCLK
INITDONE
DATAG
CEO
RDYNBSY
TDO
notes:
1. FPGA pin numbers are valid for 256-ball BGA
package.
2. Microcontroller pins are labeled according
to the digital system prototype; they are
general //O lines.
P15
C9
D8
G16
N.C.
B16
N.C.
G14
N.C.
C16
N.C.
B]
A 16
MSELO
MSEL1
TCK
P1
RI
B1 5
Figure 24: FPGA passive serial (PS) configuration circuit.
The design described thus far directly follows Altera's documentation30 (although Figure
24 shows some FPGA connections to power and ground that were not documented).
However, there are two special aspects to the TEAS FPGA configuration design.
53
nCONFIG
nSTATUS
CONFDONE
DCLK
Bit 0
DATA
Bit]
BitB
10 extra DCLK cycles required
Figure 25: FPGA passive serial (PS) configuration timing diagram.
The first unique aspect to the design arises from the length of the configuration
file for the FLEX1OK30A, which is 402,000 bits, or approximately 50 kB. Because this
file size would leave little room for the actual microcontroller program, the file is first
compressed, and the microcontroller decompresses the file as it configures the FPGA.
The output of the Altera compiler is saved as a tabular text file (.ttf) and read by a short
Java program listed in Appendix C. The program performs compression by replacing
repeating zeros with a zero followed by the additional number of zeros required. This
simple scheme cuts the 50 kB file down to approximately 20 kB. The Java program then
outputs the compressed file in a format that can be copied and pasted into the MSP430
assembly program. When running the program, the MSP430 microcontroller reads the
configuration data from its flash memory and decompresses the zeros on the fly. Because
the zeros are sent serially in a separate subroutine that just toggles the clock line the
appropriate number of times, the FPGA is configured much faster than if every zero bit
were shifted out individually. The microcontroller program that configures the FPGA is
listed in Appendix B.
The second unique aspect to the FPGA configuration scheme is that the
microcontroller receives its 8 MHz clock from the FPGA, which derives the 8 MHz clock
from a 16 MHz oscillator input. However, that 8 MHz clock is not available to the
microcontroller until after it has programmed the FPGA. The microcontroller's ability to
54
change its clock source while running is used to solve the problem. The microcontroller
initially runs off of its internal RC oscillator and configures the FPGA; the synchronous
interface to the FPGA allows the configuration to take place regardless of the exact speed
of the RC oscillator. Once the microcontroller finishes configuring the FPGA, it switches
to the 8 MHz clock provided by the FPGA.
To go into a low-power mode, the
microcontroller must switch back to RC oscillator mode before turning off the FPGA.
The assembly program listed in Appendix B configures the FPGA and then switches to
external clock mode.
The program was tested on the digital prototype described in
Section 4.
55
4. Prototypes and Results
TEAS is still far from completion, and tests of a complete unit that can be
implanted are therefore unavailable.
However, various tests of individual subsystems
have been conducted with varying degrees of success. This section will describe the
prototypes and the results of the tests on them.
December 2001 Array Implant
In December of 2001, an electrode array was implanted and tested with an
existing, external data acquisition system. While the test was meant primarily to verify
the electrode array design,
the flexible PCB was also
involved. The surgery also
exposed the members of
the TEAS
team to the
environment in which the
implant would
have to
operate and the procedure
by which it was implanted.
To be compatible
with
the
acquisition
existing
system,
data
the
array ultimately needed to
connect to an Omnetics
connector provided by the
neuroscientists
University.
at Brown
The flex-PCB
Figure 26: Flexible PCB adapter board.
was already made at this
point, so a small adapter PC board, shown in Figure 26, was made to mate with the
connector on the flex-PCB. The Omnetics connectors, which had wires on them already,
could then be soldered to the adapter board. The adapter board also had two thin wires
56
that would be placed on the surface of the brain to provide a reference point for the
signals picked up on the electrode array. The completed adapter is shown in Figure 27.
Figure 27: Adapter module for December 2001 implant (photo by Bobby Dyer). The right end
connects to the flexible PCB; the black Omnetics connectors are on the left.
The adapter assembly was then connected to the flexible PCB and secured with
epoxy, which also served as a strain relief on the Omnetics connector wires. The flexible
PCB, electrode array, and part of the adapter are shown in Figure 28. The entire module
was then covered in parylene to make it biocompatible, and shipped to Brown, where the
unit was sterilized and eventually implanted.
The surgery itself, parts of which are shown in Figures 29 through 32, provided
many insights into what would be potential problems with a fully operational, wireless
implant. Perhaps one of the biggest potential problems will be one of communication
between the teams at Brown and at MIT. This problem was evident even with the
flexible PCB, which turned out to be too long. The people at Brown had specified the
57
/
I
4
Figure 28: Test electrode array for December 2001 implant (photo by Tim Fofonoff).
length of the PCB, and they had even approved actual-size, paper models of the flexible
circuit, but the size of the real PCB in the test unit surprised them. The people specifying
the size of the PCB may have been lulled into the sense that they could get any size they
wanted, and we just had to change a few CAD parameters. This was, unfortunately, only
true until they actually specified a size; once built, the size is almost impossible to
change.
The case of the PCB being too long did not result in too large of a problem, but it
is indicative of the type of difficulty that can arise when two teams from different fields
and in different geographical locations collaborate. The surgeons performing the surgery
58
Figure 29: Surgeons attempt to permanently deform flexible PCB to conform to skull.
may not have the mentality associated with implanting not only the electrodes, but also
all of the electronics; and the people designing TEAS are not aware of all of the
surgeons' capabilities. Except for size and power considerations, the TEAS electronics
module is being treated largely as a black box that is somewhat independent of the
environment in which it must eventually operate. However, the physical structure of the
real implant will need to be closely coordinated with the surgeons to ensure that the
device is actually implantable. The angle of the flexible PCB connection to the main
unit, for example, has a big impact both on how the entire unit fits on the skull and on the
layout of the main PCB. When new members join the TEAS team to implement the fully
implantable version, it will be crucial for them to work closely with the end users, which
include both the surgeons implanting the device and the researchers using it in
experiments.
59
Figure 30: The flexible PCB is tacked down to the skull with an acrylic adhesive before the electrode
array is inserted in the brain.
One particular area that will require coordination between the Brown and MIT
teams will be in developing a procedure for connecting the main implant electronics to
the flexible PCB. The insertion of the electrode array would be much easier for the
surgeons if there were no bulky module flopping around on the other end of the flexible
PCB, but keeping open connectors clean would probably be quite difficult. Surgeons
trying to mate the two connectors would also have to prevent any stress on the inserted
electrodes, which would be especially difficult with a shorter flex-PCB. Since the test
unit implanted in December was pre-connected and the adapter board and bundle of wires
were bigger than the wireless electronics will be, pre-connecting the flexible PCB should
be acceptable.
The surgery revealed a problem with the flexible PCB besides the length being
too long: although the PCB was quite flexible, it was not malleable enough to match the
contour the surgeons wanted; the PCB would bend, but it would spring back to its
60
Figure 31: The electrode array, about to be inserted into the brain with a pneumatic insertion tool.
original shape when released. The surgeons were able to give the PCB some permanent
deformation, and, fortunately, the PCB did not prevent successful insertion of the
electrodes. In future versions, especially if the flexible PCB is shorter and permanently
attached to the electronics, a method for making a more flexible PCB will be necessary.
Although the implantation itself was successful, no neural activity could be
detected through the electrodes. Electrical impedance tests indicated some contact to
brain tissue, as did reverse experiments in which electrically stimulating the electrodes
resulted in motion in the test subject's thumb. The electrical contacts indicate that the
initial array probably failed due to defects in the construction of the array rather than
because of problems in the interconnection system. This conclusion was supported by
evaluation of the array itself, which was eventually retrieved, but the flexible PCB and
the Omnetics adapter board assembly were destroyed, eliminating the possibility of
analyzing the wiring.
61
Figure 32: The entire assembly is covered with an acrylic adhesive.
62
Digital Prototype
A prototype printed circuit board containing the major digital elements, the
FPGA, microcontroller, and SRAMs, was created to test the digital system design.
Although some limited VHDL tests were run on simple breadboard circuits, and other
VHDL sections were tested in simulation, the majority of physical tests were conducted
on this prototype. The digital prototype does not exactly represent a design that would be
implemented on an implantable unit, and all of the tests possible with the given
connections have not yet been conducted.
However, the most important system-
integration aspect of the design, the configuration of the FPGA by the microcontroller
and the accompanying clocking scheme, has been verified.
One of the greatest difficulties in creating a prototype quickly, and at a reasonable
cost, was dealing with the small device sizes in the design. In particular, the BGA (ball
grid array) packages of the FPGA and the spike detection system's SRAM are almost
impossible to use without manufacturing multi-layer PCBs with very fine traces.
Soldering the devices also requires special equipment that was not readily available. The
SRAM was therefore omitted from the digital prototype, and a similar SRAM, although
with only an 8-bit data bus, was used instead. Such a substitution was not possible with
the FPGA since it is the primary component in the system and an identical component
with a different package is not available. Instead, a zero insertion force (ZIF) socket
from Emulation TechnologyI (part number AB2563BG16P13M1) was used. The ZIF
socket allows the FPGA to be locked into place without any soldering, and the other end
of the socket has a pin grid array with a standard 0.1" (2.54 mm) spacing. With the ZIF
socket, the digital prototype could be made with a standard, 2-layer printed circuit board.
The component placement of the digital prototype is shown in Figure 33. Beside
the four integrated circuits, the board has the circuitry necessary for reprogramming the
microcontroller, including a socket for the microcontroller programmer, the FPGA
configuration circuit shown in Figure 24, a 16 MHz oscillator, and connectors for
connecting to a prototype ADC board. Because the FPGA has more than enough 1/0
63
test point bank F
test point bank E
0.1 uF
cap
/
test point
bank D
JTAG interface
connector for
microcontroller
reprograming
00 EQ
00
00
00
test point bank C
0.
4S
S
00
0
00
0
000
-L
test point bank B
0000
ii
rA
FPGA
configuration
pull-up resistors
0
/
0.1 uF
cap
0000000
00000000
0000
0000
0000
0000
0000
0000
0000
0000
00000
0000000000
0000000000
0000000000
000000000
0
0
---16 MHz
oscillator
0A
00000
0000000
clock select
jumpers
0000
0000
0000
0000
0000
O
0000
0000
00000
00000000
000000001 v
I
0000000000
0000000000
0000000000
000000000
oOO
000
00
00
00
00
0
0
test point
bank I
test point
bankJ
00000000
00000000
00000000
00000000
I
/
ADC board
connector 1
uF cap
0.1 uFcap
00
00000
00
MSP430F149
microcontroller
00
3V power in
-10
00
000
00
00000000000000000000
0000000000000000
00
00O
02
00o
00
000000 000
00000000
000 000
0000000000
0
test point bank A
I
0
0 00
microcontroller
programming
pull-up resistor
~
/
_
00
00
0
test point
bank G
2Mx8SRAM
00000000
00000000]
00
test point
bank H
0.1 uF
cap
ADC board
connector 2
64k x 8 SRAM
EPF1OK30A
FPGA
Figure 34: Layout of top layer of digital prototype PCB.
lines, every I/O pin on the SRAMs, including inputs such as chip-enable lines that would
be permanently enabled in the final implant, is connected to an FPGA I/O line. Two 8-bit
I/O ports on the microcontroller are also connected to general I/O lines on the FPGA.
Every one of these data lines is brought out to a test point to facilitate debugging. The
FPGA has two dedicated clock inputs; jumpers on the oscillator allow the clock to be
directed to either input.
The PCB traces for the top and bottom layers are shown in Figure 34 and Figure
35, respectively. Even without BGA components, fine traces are required because of the
0.5 mm pitches of the SRAMs and microcontroller. The flexibility of the FPGA I/O lines
made the layout straightforward since individual connections between the FPGA and
65
'00
00
*6
000
000
*0
0
0
*099
09000099voo
0
00009009009V1
/
0* @o
0 9*
*0..
q 4ro 0
@
0*0
00000
09
0ei
90
*oj*9990
09*00
009
900
0fi*
0
Figure 35: Layout of bottom layer of digital prototype PCB.
other components were determined solely by trace routing considerations. Because only
approximately 50% of the FPGA will be used, and because it is running at relatively slow
speeds, arbitrary assignment of signals to physical pins should not be an issue. On a final
design, with more PCB layers available, it will be possible to make more carefully chosen
pin assignments that take into consideration the function of the assigned signal.
The digital prototype PCB has been built and assembled; the completed board is
shown in Figure 36. (The PCB was machined rather than etched, leaving copper areas
that are electrically isolated.) The surface-mounted components were soldered using
solder paste and a hot-air soldering pencil.
The lack of a solder mask makes the
prototype more vulnerable to shorts during soldering, and although some components
66
have not been tested functionally, the integrity of all electrical connections has been
verified.
Figure 36: The fully assembled digital prototype.
Using the digital prototype board, the most important integration aspect of the
design, the configuration of the FPGA through the microcontroller, has been fully
verified. The JTAG interface allows the microcontroller to be reprogrammed, and a test
program consisting of the global counter and ADC interface has been run on the FPGA.
Figure 37 shows a logic analyzer screen shot showing the ADC interface serial clock and
the eight staggered serial control signals. Similar analysis of the microcontroller outputs
showed that the configuration and clock-changing (from internal RC to FPGA-supplied 8
MHz) program listed in Appendix B is fully functional.
67
Figure 37: Logic analyzer screen shot showing ADC serial clock and eight serial control signals
staggered by 2 clock cycles.
Although the digital prototype board is fully assembled, the SRAMs have not yet
been tested with the FPGA. The ADCs have also not been run with the FPGA because
the prototype PCB carrying a bank of ADCs is not yet completed. However, individual
tests with through-hole components with similar interfaces have indicated that the
memory access and ADC interface VHDL code works. A full, integrated test of the
entire digital system would be somewhat reassuring, but with the complete flexibility and
reprogrammability of the FPGA, the details of the digital design can be adapted readily
for implementation in a final, implantable version. As Figure 38 shows, a final design
must be considerably smaller than the digital prototype. However, the digital prototype
can continue to be useful since it will allow for refinements to the digital system software
to be made while the final implant is being manufactured.
68
Figure 38: The digital prototype is not ready for implanting, yet...
The Rest of TEAS
The final implant will require full integration of the TEAS electronics, including
the analog section. Because the December array implant did not provide a useful test
case for the electronics, the analog section will have to be tested independently of the
electrodes being designed for TEAS. Preliminary tests of existing electrodes were not
successful due in part to difficulties in connecting analog electronics prototypes to the
existing electrode arrangements at Brown. To speed up testing, which can be difficult to
schedule when performed on live monkeys, the amplifier design was tested with neuron
simulation circuits such as those shown in Figure 39. Even with these simple, resistordivider circuits, the operation of the amplifiers could not be completely verified. The
amplifier performed as desired on the straight voltage divider, but adding an RC
component in series with the signal to be amplified caused unacceptable noise on the
amplifier output. Additional tests will be performed on real brains, possibly using rats, to
gain more conclusive evidence about the performance of the analog section.
69
Function
Generator
Function
Generator
Figure 39: Neural simulator circuits used to test amplifier circuit.
A prototype Bluetooth interface is fully functional, with a microcontroller
wirelessly sending data to a PC. However, the maximum achievable data rate, at around
500 kbps, falls short of the theoretical maximum of over 700 kbps.
The theoretical
maximum may not be achievable in an electrically noisy lab setting, but the digital
section of TEAS is flexible enough to provide useful data at lower data rates.
The
software running on the PC is a simple Java program that allows for connecting to a
wireless device and reading back information; more sophisticated software will be
necessary to support the final implant's configuration options and to read and display
recorded data.
70
5. Conclusion
The TEAS electronics design presented here should meet all of the original
project requirements. An implant based on this design should be able to run for several
hours while wirelessly transmitting neural data to an external data logging system. All
necessary components have been selected and obtained, and they are small enough for the
complete system to fit in a 50 mm x 50 mm x 10 mm container. The most critical
aspects of the system have been implemented as prototypes, and their required
performance has been confirmed.
However, three substantial tasks must still be
completed before a viable implant that outperforms existing systems is ready:
" System integration;
*
External interface software;
" Encapsulation for implantation.
System Integration
The major system blocks, the analog electronics, digital electronics, wireless
interface, and power system have been developed and tested independently.
These
systems will have to be integrated into a single design, which will require additional
software work on the microcontroller and substantial work in layout and manufacturing.
The entire implant electronics will occupy at least two printed circuit boards that are
populated on both sides. The layout will be very dense, probably requiring the PCBs to
have at least six layers routed with 5-mil (125 rim) traces32 . The small footprints and
double-sided assembly will require state-of-the-art electronics manufacturing technology.
In general, most of the work in shrinking the design to fit in the required space will
involve coordination with PCB and electronics manufacturers rather than extensive
design work; however, the wireless recharging system still requires substantial design
work.
External Interface Software
No user interface for displaying neural signals or configuring the implant exists at
71
this point. The existing system at Brown, on the other hand, has a beautiful interface that
would require a tremendous amount of effort to match. Even if it is wireless, TEAS will
not be better than existing, tethered systems without an interface that is readily accessible
to researchers. The minimum requirements for the TEAS user interface software are:
*
Hardware drivers for wireless interface hardware. Some form of Bluetooth
transceiver, possibly in PC card format, will be necessary for the external PC to
communicate with the implant.
The external system software will need to
communicate with the transceiver at a high speed and in real time.
*
The user interface must allow simple
Implant configuration interface.
configuration of implant parameters such as triggering thresholds and the number
of samples to store for each spike. This interface should be graphical, and there
should be support for saving and recalling implant configurations.
*
Waveform display in real time. The current data acquisition system provides
researchers graphical representations of neural activity as it occurs.
Although
great graphics are not crucial, the interface should not be substantially inferior to
the systems to which the researchers are accustomed. The graphical interface also
gives researchers real-time feedback about the effectiveness of their experimental
setup.
*
Saving data. The external software must log all data for later analysis. Multiple
output formats should be supported, and although the different file formats might
not have to be generated directly by the software, the process for loading the data
into other programs must be straightforward.
Encapsulation for Implantation
Once the electronics are assembled, they will need to be mechanically housed in a
package that is both biocompatible and resistant to the corrosive fluids in the brain. The
method of connection to the electrode array, and to the battery pack to be installed in the
abdomen, must be determined.
If the electrode-carrying flexible PCB is permanently
attached to the primary electronics, it might be more appropriate to eliminate the
72
connector altogether and make a hybrid PCB that has a rigid portion for the main
electronics and a flexible portion for connecting to the array. The final packaging will
have to be closely coordinated with the surgeons performing the implantation to ensure
that the device will fit properly.
Future Direction of TEAS and Wireless Implants
The future of wireless implants is clearly in very large-scale integration (VLSI),
whereby the entire design is made on a single, custom, integrated circuit 33 . Such an
approach will result in much smaller, less power-hungry devices, and it also scales much
better than the TEAS design and its discrete components, which are appropriate only on
very early designs.
The TEAS electronics are already very large compared to the
electrode array, and the electronics size will grow with the number of channels required.
With the custom integrated circuit, on the other hand, the electronics can be present on
the back of the array, and the implant will take no more space than the array itself; thus, if
there is physical space on the brain for additional or larger arrays, the electronics will fit
as well.
Our colleagues at Brown University are already working on such a VLSI
system.
With TEAS still requiring much work before implantation, it is unclear that the
COTS component aspect of the project is worth pursuing further. Although the TEAS
electronics system itself is much cheaper to manufacture than a custom integrated circuit,
the electronics alone is worthless without a good external software interface.
When
including the cost of development of necessary software support and considering that the
manufacturing costs do not decrease substantially for producing additional units, as they
do with custom integrated circuits, TEAS is still very expensive. Even though the intent
of the project is not to be mass-producing brain implants, several units are desirable even
in a test implant. The support software costs would be necessary for any implant, but the
hardware development costs become a smaller portion of the overall cost. A TEAS
approach is still cheaper, but not by a significant factor, and a VLSI approach will result
in a much superior implant.
Despite this somewhat bleak outlook, not all of the work on TEAS has been in
73
vain.
Even with custom integrated circuits, many modules are taken from existing
component designs or intellectual property function blocks. A combination of the VLSI
and COTS approach may also be appropriate since some COTS performance will be
difficult to beat.
In a mixed design, a custom IC might hold all amplifiers and
multiplexers while a commercial ADC and microcontroller was used for signal
processing.
The components used in TEAS were chosen for their remarkable
performance, and they can serve as a benchmark when designing a VLSI system.
The
problems of limited communication bandwidth will not go away with VLSI since
building a radio better than the Bluetooth module is unlikely; with limited bandwidth, the
spike detection techniques used in TEAS are still relevant. The TEAS digital system
design also has the tremendous advantage of being completely reconfigurable, even while
implanted. Thus, TEAS could serve as a good initial test platform that is flexible enough
to deal with unforeseen problems. Even if TEAS is never fully built and implanted, its
design can serve as a starting point and reference for smaller and better brain implants of
the future.
74
References
1.
Kennedy, P.R. and Bakay, R.A. NeuroReport 9, pp. 1707-1711. 1998.
2.
Martinerie, J., Adam, C., Le Van Quyen, M., Baulac M., Clemenceau S., Renault, B., and
Varela, F.J. Epileptic seizures can be anticipated by nonlinear analysis. Nature Medicine
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Serruya, M., Hatsopoulos, N., Paninski, L., Fellow, M., and Donoghue, J. Instant neural
control of a movement signal. Nature 416, pp. 141-142. 2002.
Maynard, E., Hatsopoulos, N., Ojakangas, C., Acuna, B., Sanes, J., Normann, R., and
Donoghue, J. Neuronal Interactions Improve Cortical Population Coding of Movement
Direction. J ofNeuroscience 19, pp. 8083-8093. 1999.
Martel, S., Hatsopoulos, N., Donoghue, J., Hunter, I., Burgert, J., Malasek, J., Wiseman,
C., and Dyer, R. Development of a Wireless Brain Implant: the Telemetric Electrode
Array System (TEAS) Project. Proceedings of the 2 3rd Annual International Conference
of the IEEE Engineering in Medicine and Biology Society, Istanbul, Turkey. Oct. 25-28,
2001.
6.
Fofonoff, T., Wiseman, C., Dyer, R., Malasek, J., Burgert, J., Martel, S., Hunter, I.,
Hatsopoulos, N., and Donoghue, J. Mechanical Assembly of a Microelectrode Array for
use in a Wireless Intracortical Recording Device. Proceedings of 2 "d International IEEEEMBS Special Topic Conference on Microtechnologies in Medicine and Biology.
Madison, WI. May 2-4, 2002.
7.
8.
9.
Molex Inc., Lisle, IL, USA. Web page: http://www.molex.com/.
Molex Inc. 0.50mm (.020") Pitch SlimStack Plug datasheet. [Online datasheet] available
HTTP: http://www.molex.com/product/micro/53794.html [available May 2001]
Burgert, J., Malasek, J., Martel, S., Wiseman, C., Fofonoff, T., Dyer, R., Hunter, I.,
Hatsopoulos, N., and Donoghue, J. Embedded Electronics for a 64-Channel Wireless
Brain Implant. Proceedings of SPIE: Microrobotics and Microassembly, Newton, MA.
Oct. 29-31, 2001.
10. Maxim Integrated Products, Inc., Sunnyvale, CA, USA. Web page:
http://www.maximic.com/.
11. Maxim Integrated Products. Max1280/MAX1281. Publication 19-1684; Rev 0.
http://www.maximic.com. 2000.
12. The Bluetooth Special Interest Group. Specification of the Bleutooth System-core.
Version 1.1 http://www.bluetooth.com. 2001.
13. Cambridge Silicon Radio. BlueCore0l Single Chip Bluetooth System. Publication
BCLF1901/1. http://www.cambridgesiliconradio.com. 2000.
14. Burgert, J. Telemetric Brain Electrode Array: Wireless and Analog Systems. M. Eng.
Thesis MIT EECS. May, 2002.
15. Atmel Corporation, San Jose, CA, USA. Web page: http://www.atmel.com/.
16. Atmel Corporation. FPSLIC Product Overview. [Online document] Available HTTP:
http://www.atmel.com/atmel/products/prod39a.htm [available May 2001].
17. Ziv, J. and Lempel, A. A Universal Algorithm for Sequential Data Compression. IEEE
Transactionson Information Theory, Vol. 23, pp. 337-342. 1977.
18. Xilinx, Inc., San Jose, CA, USA. Web page: http://www.xilinx.com/.
19. Cypress Semiconductor Corporation, Palo Alto, CA, USA. Web page:
http://www.cypress.com/.
20. Altera Corporation, San Jose, CA, USA. Web page: http://www.altera.com/.
21. Altera Corporation. Flex 10K Embedded Programmable Logic Device Family Datasheet.
Publication A-DS-F1OK-04.1. March 2001.
75
22. Digi-Key Corporation, Thief River Falls, MN, USA. Web page:
http://www.digikey.com/.
23. Toshiba America Electronics Components, Inc., Irvine, CA, USA. Web page:
http://www.toshiba.com/taec/.
24. Toshiba Corporation. TC55W1600FT-55,-70 Datasheet (Tentative). Publication
000707EBA2. October 2000.
25. Cypress Semiconductor Corporation. CY62126BV Datasheet. June 2000.
26. Microchip Technology Inc., Chandler, AZ, USA. Web page:
http://www.microchip.com/1010/index.htm.
27. Texas Instruments Incorporated, Dallas, TX, USA. Web page: http://www.ti.com/.
28. Texas Instruments. MSP430xl3x, MSP430xl4x Mixed Signal Microcontroller.
Publication SLAS272C rev Feb 2001. http://www.ti.com. 2000.
29. Texas Instruments. MSP430xlxx Family User Guide. Publication SLAU049. 2000.
30. Altera Corporation. Application Note 116: Configuring SRAM-Based LUT Devices.
Publication A-AN-116-2.0. June 2001.
31. Emulation Technology, Inc., Santa Clara, CA, USA. Web page:
http://www.emulationtechnology.com/
32. Altera Corporation. Application Note 114: Designing with FineLine BGA Packages.
Publication A-AN- 114-01.03. November 1999.
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Moxon, K.A.) CRC., Boca Raton. 2000.
76
Appendix A: VHDL Code
This appendix contains the six VHDL source files that specify the logic
implemented in the Altera FLEX1OK30A FPGA. Because TEAS is not complete at the
time of this writing, some of the details of the code continue to change; the files included
here are intended to be the most current, running versions of the design. The six files are:
"
"
"
*
*
"
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Al:
A2:
A3:
A4:
A5:
A6:
Spike Detection System VHDL Source: ringbuf.vhdl
Transmit Buffer Control VHDL Source: bigbuf.vhdl
ADC Serial Interface Input Control VHDL Source: serin.vhd
ADC Serial Interface Output Control VHDL Source: serout.vhd
Global Counter VHDL Source: cntr.vhd
TEAS Integration VHDL Source: teas.vhd
Appendix Al: Spike Detection System VHDL Source: ringbuf.vhdl
--
module that controls the 64 ring buffers for prestore
--
there are five latched values; the pairs are given below:
nextstate, presentstate: for main state machine
nextaddrl, addr: nextaddrl is the next (6) low bits of addr
nextstatus, STATUS: 16-bit STATUS for each channel
nextresult, result: outputs from buffer reads
nextresultValid, resultValid: set when result has valid value
------
library IEEE;
use IEEE.std logic_1164.all;
--use IEEE.numeric std.all;
use IEEE.stdlogic arith.all;
package ringbufpckg is
component ringbuf is
port (
clk, reset: in std logic;
RW: buffer stdlogic;
-- 1 = read, 0 = write
nOE, nCE: out stdlogic;
addrh: in stdlogic-vector(5 downto 0);-- chan #, bits 7-2 of glob. counter
countl: in stdlogic vector(l downto 0);-- two lowest bits of glob. counter
addr: out std_logic-vector(11 downto 0);
sample: in stdlogic-vector(11 downto 0);
result: out stdlogic vector(11 downto 0);
resultValid: out std logic;
-- set to indicate valid result
datapins: inout std logicvector(13 downto 0);
-- actual I/O pins
-- upper 24 bits of global counter
time: in stdlogic-vector(23 downto 0);
-- pins for microcontroller parameter access
uCaddr: in std logic vector (7 downto 0) ;
uCdata: in stdlogicvector(ll downto 0);
uCwr: in stdlogic;
uCmode: in std_logic;
-- pins for setting up number of samples per trigger
77
bufSizeIn:
in std logic_vector(2 downto 0);
loadBufSize:
in std logic
end component;
end ringbuf_pckg;
library IEEE;
use IEEE.stdlogic 1164.all;
--use IEEE.numericstd.all;
use IEEE.stdlogic arith.all;
entity ringbuf is
port (
clk, reset: in std logic;
-- 1 = read, 0 = write
RW: buffer std_logic;
nOE, nCE: out stdlogic;
7-2 of glob. counter
addrh: in std_logicvector(5 downto 0);-- chan #, bits
countl: in std_logic vector(l downto 0);-- two lowest bits of glob. counter
addr: out stdlogic_vector(11 downto 0);
sample: in std_logicvector(11 downto 0);
result: out stdlogic vector(ll downto 0);
-- set to indicate valid result
resultValid: out stdlogic;
-- actual I/O pins
datapins: inout std logic_vector(13 downto 0);
-- upper 24 bits of global counter
time: in stdlogic vector(23 downto 0);
-- pins for microcontroller parameter access
uCaddr: in stdlogicvector(7 downto 0);
uCdata: in stdlogicvector(ll downto 0);
uCwr: in stdlogic;
uCmode: in std_logic;
-- pins for setting up number of samples per trigger
bufSizeIn: in std logic_vector(2 downto 0);
loadBufSize: in std logic
end ringbuf;
architecture archringbuf of ringbuf is
type StateType is (idle,
readSTATUS,
readTRIG, readUNTRIG, readPOSTSTORE, getChanl, getTimel,
readl,
--
--
writeSample, getChan2, getTime2, read2,
writeSTATUS,
errorState);
signal present_state, next-state : StateType;
signal nextaddrl: stdlogic vector(5 downto 0);
signal STATUS, nextstatus : std_logic vector(13 downto 0);
intention to write, ORed with clk to get RW
-signal nwrite: std_logic;
signal data: stdlogic vector(13 downto 0);
signal nextresult: stdlogicvector(11 downto 0);
signal nextresultValid: std logic;
signal threshExceeded : stdlogic;
signal bufSize: std logicvector(2 downto 0);
channelState is saved in STATUS for each state; this alias valid only
during readSTATUS
alias channelState : std_logic vector(1 downto 0) is datapins(13 downto 12)
a channel can be in one of four states:
: stdlogicvector(l downto 0) := "00";
constant untriggered
: stdlogicvector(l downto 0) := "01";
constant triggered
78
constant readSamples
constant sendChanInfo
stdlogic vector(1 downto 0) :"10';
stdlogic
vector(l downto 0) :="11";
begin
statecomb:process(presentstate, reset, datapins, STATUS, countl,
threshExceeded, sample, addrh, nextaddrl,
uCaddr, uCdata, uCwr, uCmode,
bufsize, time)
begin
-- reset
-DONE 010619
if (reset = '1') then
nextstate <= idle;
nextaddrl <= (others => '');
nextstatus <= (others => '-');
-STATUS undefined during reset
nextresult <= (others => '-');
-no result during reset
nextresultValid <= '0';
data <= (others => '-');
nwrite <= '1';
nOE <= '0';
-microcontroller override
-DONE 010619
elsif (uCmode = '1') then
-- need to reset big buffer
nextstate <= idle;
nextaddrl <= "0000" & uCaddr(l downto 0);
nextstatus <= (others => '-');
nextresult <= (others => '-');
nextresultValid <= '0';
data <= "00" & uCdata;
if(uCwr = '1') then
nwrite <= '0';
nOE <= '1';
else
nwrite <= '1';
nOE <= '0';
end if;
else
case present-state is
-idle
-DONE 010619
when idle =>
if (countl = "11") then
-get in sync with global counter
nextstate <= readSTATUS;
else
nextstate <= idle;
end if;
nextaddrl <= (others => '0');
nextstatus <= (others =>
nextresult <= (others =>
nextresultValid <= '0';
data <= (others => '-');
nwrite <= '1';
nOE <= '0';
---
readSTATUS
DONE 010619
when readSTATUS =>
case channelState is
when untriggered =>
79
-- read THRESHOLD, store sample, check for trigger
STATUS.counter(0) is being used
-if(datapins(0) = '0') then
to check for untriggering
-nextstate <= readTRIG;
-location of THRESHOLD
nextaddrl <= "000001";
else
nextstate <= readUNTRIG;
nextaddrl <= "000011";
end if;
when triggered =>
read POSTSTORE, store sample, increment STATUS.address
-decrement STATUS.counter
-nextstate <= readPOSTSTORE;
-- location of POSTSTORE
nextaddrl <= "000010";
when sendChanInfo =>
-send the channel number in one cycle and the
time in the next cycle
--- STATUS.counter(0) is being used
if(datapins(0) = '0') then
to check if channel number has
-nextstate <= getChanl;
been sent
-else
nextstate <= getTimel;
end if;
don't need to access memory
-nextaddrl <= (others => '-');
when readSamples =>
read two samples, incrementing STATUS.address and
--decrementing STATUS.counter
nextstate <= readl;
nextaddrl <= datapins(11 downto 6);
when others =>
next state <= errorState;
nextaddrl <= (others =>
end case;
nextstatus <= datapins;
nextresult <= (others =>
nextresultValid <= '0';
data <= (others => '-');
nwrite <= '1';
nOE <= '0';
---
--save channel STATUS
readUNTRIG
DONE 010625
when readUNTRIG =>
nextstate <= writeSample;
nextaddrl <= STATUS(11 downto 6);
if(STATUS(11 downto 6) = "111111") then
nextstatus(11 downto 6) <= bufSize & "100";
else
nextstatus(11 downto 6) <=
UNSIGNED(STATUS(11 downto 6)) + 1;
end if;
if(threshExceeded <= '1') then
nextstatus(13 downto 12) <= "00";
nextstatus(5 downto 0) <= "---1";
else
nextstatus(13 downto 12) <= "00";
nextstatus(5 downto 0) <= "-----0";
end if;
nextresult <= (others => '-');
80
nextresultValid <= '0';
data <= (others => '-');
nwrite <= '1';
nOE <=
--
-----
readTRIG
DONE 010625
when readTRIG =>
nextstate <= writeSample;
nextaddrl <= STATUS(11 downto 6);
if(STATUS(l1 downto 6) = "111111") then
nextstatus(l1 downto 6) <= bufSize & "100";
else
nextstatus(11 downto 6) <=
UNSIGNED(STATUS(ll downto 6)) + 1;
end if;
if(threshExceeded <= '1') then
if(bufSize = "111") then
nextstatus(13 downto 12) <= "11";
nextstatus(5 downto 0) <= "----10";
else
nextstatus(13 downto 12) <= "01";
nextstatus(5 downto 0) <= "000000";
end if;
else
nextstatus(13 downto 12) <= "00";
nextstatus(5 downto 0) <= "-----0";
end if;
nextresult <= (others => '-');
nextresultValid <= '0';
data <= (others =>
nwrite <= '1';
nOE <=
readPOSTSTORE
DONE 010620
all
ones ("111111") in STATUS.counter means that this
is the first
time
In that case, the number
this state is entered after triggereing.
of poststores is loaded from address 2; this value should be 0-62.
The actual number of poststores is one greater than POSTSTORE.
STATUS.address, as always, gets incremented and wraps from 63 to 4.
when readPOSTSTORE =>
-POSTSTORE is read on every sample write after triggering.
It
-is only used if the STATUS.counter is zero, in which case the
-counter is set to POSTSTORE.
If POSTSTORE were zero, the
-channel would get stuck in a poststore loop, which is one way
-of disabling a channel.
In general, the counter is incremented
-with every sample that is stored, until the counter reaches
-"111111", at which point the send channel data mode is
-entered.
nextstate <= writeSample;
nextaddrl <= STATUS(l1 downto 6);
if(STATUS(11 downto 6) = "111111") then
nextstatus(11 downto 6) <= bufSize & "100";
else
nextstatus(ll downto 6) <=
UNSIGNED(STATUS(11 downto 6)) + 1;
end if;
if(STATUS(5 downto 0) = "000000") then
nextstatus(5 downto 0) <= datapins(5 downto 0);
nextstatus(13 downto 12) <= "01";
81
elsif(STATUS(5 downto 0) = "111111") then
nextstatus(5 downto 0) <= "----00";
nextstatus(13 downto 12) <= "11";
else
downto 0) <= UNSIGNED(STATUS(11
nextstatus(5
nextstatus(13 downto 12) <= "01";
end if;
nextresult <= (others => '
nextresultValid <= '0';
data <= (others => '-');
nwrite <= 1';
nOE <= '-';
---
getChanl
DONE 010619
when getChanl =>
nextstate <= getChan2;
nextaddrl <= (others =>
nextstatus <= STATUS(13 downto 1) & '1';
nextresult <= (others => '0');
nextresultValid <= '1';
data <= (others =>
nwrite <= '1';
nOE <= '-';
--
downto
+ 1;
channel number sent
---
getTimel
DONE 010626
when getTimel =>
nextstate <= getTime2;
nextaddrl <= (others =>
nextstatus(l downto 6) <= STATUS(ll downto 6);
-- timestamp mode
if(STATUS(l) = '1') then
nextstatus(13 downto 12) <= "00";
nextstatus(5 downto 0) <= "-----1";
else
nextstatus(13 downto 12) <= "10";
nextstatus(5 downto 0) <= "000000";
end if;
nextresult <= time(23 downto 12);
nextresultValid <= '1';
data <= (others => '-');
nwrite <= '1';
nOE <=
---
readl
DONE 010626
when readl =>
nextstate <= read2;
if(STATUS(11 downto 6) = "111111") then
nextaddrl <= bufSize & "100";
else
nextaddrl <= UNSIGNED(STATUS(11 downto 6)) + 1;
end if;
if(STATUS(ll downto 6) = "111111") then
nextstatus(ll downto 6) <= bufSize & "101";
elsif (STATUS(11 downto 6) = "111110") then
nextstatus(ll downto 6) <= bufSize & "100";
else
next status(11 downto 6) <=
UNSIGNED(STATUS(11 downto 6)) + 2;
end if;
82
6))
if(STATUS(5
downto 0) = "000000") then
setting STATUS.counter to bufSize & "111" gets the right number
-of samples read since four extra sample readings occur: two in
-the cycle when counter is first set, and two in the cycle where
-counter reaching "111111" is detected.
nextstatus(13 downto 12) <= "10";
nextstatus(5 downto 0) <= bufSize & "111";
elsif(STATUS(5 downto 0) = "111111") then
next status(13 downto 12) <= "00";
nextstatus(5 downto 0) <= "---1";
else
nextstatus(13 downto 12) <= "10";
nextstatus(5 downto 0) <=
UNSIGNED(STATUS(5 downto 0)) + 1;
end if;
nextresult <= datapins(ll downto 0);
nextresultValid <= ''
data <= (others =>
nwrite <= '1';
nOE <= '0';
--
---
---
---
getChan2
DONE 010619
when getChan2 =>
nextstate <= writeSTATUS;
nextaddrl <= (others => '0');
nextstatus <= STATUS;
nextresult <= "000000" & addrh;
nextresultValid <= '1';
data <= (others =>
nwrite <= '1';
nOE <= '-';
writeSample
DONE 010619
when writeSample =>
nextstate <= writeSTATUS;
nextaddrl <= (others => '0');
nextstatus <= STATUS;
nextresult <= (others =>
nextresultValid <= '0';
if(sample = "000000000000") then
data <= "--000000000001";
else
data <= "--"
& sample;
end if;
nwrite <= '0';
nOE <= '1';
getTime2
DONE 010626
when getTime2 =>
nextstate <= writeSTATUS;
nextaddrl <= (others => '0');
nextstatus <= STATUS;
nextresult <= time(11 downto 0);
nextresultValid <= '1';
data <= (others =>
nwrite <= '1';
nOE <= '-';
83
---
nudge a sample of zero a little
since zero is sync value
---
read2
DONE 010626
when read2 =>
nextstate <= writeSTATUS;
nextaddrl <= (others => '0');
nextstatus <= STATUS;
nextresult <= datapins(11 downto 0);
nextresultValid <= '1';
data <= (others =>
nwrite <= '1';
nOE <= '0';
--
writeSTATUS
DONE 010619
when writeSTATUS =>
next state <= readSTATUS;
'');
nextaddrl <= (others =>
nextstatus <= (others =>
nextresult <= (others =>
nextresultValid <= 'o';
data <= STATUS;
nwrite <= '0';
nOE <= '1';
--
--
errorState
DONE 010619
when errorState =>
nextstate <= errorState;
nextaddrl <= (others =>
nextstatus <= (others =>
nextresult <= (others =>
nextresultValid <= '0';
data <= (others => '-')
nwrite <= '0';
nOE <= '1';
when others =>
nextstate <= errorState;
nextaddrl <= (others =>
nextstatus <= (others =>
nextresult <= (others =>
nextresultValid <= '0';
data <= (others => '-');
nwrite <= '0';
nOE <= 'l';
end case;
end if;
end process statecomb;
stateclocked:process(clk, uCmode, loadBufSize)
begin
if(clk'event and clk = '1') then
presentstate <= nextstate;
STATUS <= nextstatus;
if(uCmode = '1') then
addr <= uCaddr(7 downto 2) & nextaddrl;
else
addr <= addrh & nextaddrl;
84
end if;
result <= nextresult;
resultValid <= nextresultValid;
if(loadBufSize = '1') then
bufSize <= bufSizeIn;
else
bufSize <= bufSize;
end if;
end if;
end process stateclocked;
output enable: process
(RW, data)
begin
if RW =
I'l
then
datapins <=
(others =>
'Z');
else
datapins <= data;
end if;
end process output-enable;
checkthresh: process(sample, datapins)
begin
if(sample > datapins(11 downto 0)) then
threshExceeded <= '1';
else
threshExceeded <= '0';
end if;
end process checkthresh;
nCE <=
'0';
--
temporary, for use with XS95 board
RW <= nwrite or clk;
---
allows write per clock cycle
requires clock low time to be at least 50 ns
end archringbuf;
85
Appendix A2: Transmit Buffer Control VHDL Source: bigbuf.vhdl
---
module that controls the large memory used to store
data that is to be sent out over the Bluetooth line
library IEEE;
use IEEE.stdlogic 1164.all;
use IEEE.stdlogic arith.all;
package bigbufpckg is
component bigbuf
generic (
addrlines: integer := 2);
port (
-- internal connections to other VHDL modules
clk, reset: in std logic;
countl: in stdlogic vector(l downto 0);--two lowest bits of global counter
sample: in stdlogicvector(ll downto 0);
validIn: in std_logic;
-- connections to buffer SRAM
RW: buffer stdlogic;
nOE, nCE: out stdlogic;
addr: out stdlogicvector(addrlines-1 downto 0);
datapins: inout std logicvector(7 downto 0);
-- connections to microcontroller
overflow, newdata : out std logic;
ack: in std logic;
result: buffer std logic_vector(7 downto 0)
end component;
end bigbuf_pckg;
library IEEE;
use IEEE.stdlogic 1164.all;
use IEEE.stdlogic arith.all;
entity bigbuf is
generic (
addrlines: integer
:= 4);
port (
-- internal connections to other VHDL modules
clk, reset: in std logic;
countl: in stdlogic vector(l downto 0);--two lowest bits
sample: in stdlogic vector(11 downto 0);
validIn: in std_logic;
-- connections to buffer SRAM
RW: buffer std_logic;
nOE, nCE: out std logic;
addr: out stdlogic vector(addrlines-1 downto 0);
datapins: inout std logicvector(7 downto 0);
-- connections to microcontroller
overflow, newdata : out std logic;
ack: in std logic;
result: buffer std logic_vector(7 downto 0)
end bigbuf;
86
of global counter
architecture archbigbuf of bigbuf is
signal readaddr: stdlogic vector(addrlines-1 downto 0);
signal writeaddr, nextwriteaddr: stdlogic vector(addrlines-1 downto 0);
signal update_out: std logic;
signal convBuf, nextconvBuf: std_logicvector(7 downto 0);
signal
signal
signal
signal
data: stdlogicvector(7 downto 0);
nwrite: std_logic;
sampleValid, nextsampleValid: stdlogic;
nextresult:
std logic_vector(7 downto 0);
begin
process(countl, sample, convBuf, validIn, sampleValid,
writeAddr, readAddr, dataPins, result)
begin
case countl is
when "00" =>
data <= convBuf;
nextconvBuf <= "--------";
next sampleValid <= '-';
addr <= writeAddr;
if(sampleValid = '1') then
nextwriteAddr <= UNSIGNED(writeAddr) + 1;
nwrite <= '0';
else
nextwriteAddr <= writeAddr;
nwrite <= '1';
end if;
nextresult <= result;
when "01" =>
data <= "--------"1;
nextconvBuf <= "--------";
next sampleValid <= '-';
addr <= readAddr;
nextwriteAddr <= writeAddr;
nwrite <= '1';
nextresult <= datapins;
when "10" =>
-- 12-bit sample 1 available now
data <= sample(7 downto 0);
nextconvBuf <= "----"
& sample(ll downto 8);
next sampleValid <=
addr <= writeAddr;
if(validIn = '1') then
nextwriteAddr <= UNSIGNED(writeAddr) + 1;
nwrite <= '0';
else
nextwriteAddr <= writeAddr;
nwrite <= '1';
end if;
nextresult <= result;
when "11" =>
-- 12-bit sample 2 available now
data <= sample(3 downto 0) & convBuf(3 downto 0);
nextconvBuf <= sample(1l downto 4);
next sampleValid <= validIn;
addr <= writeAddr;
if(validIn = '1') then
nextwriteAddr <= UNSIGNED(writeAddr) + 1;
nwrite <= '0';
else
87
nextwriteAddr <= writeAddr;
nwrite <= '1';
end if;
nextresult <= result;
when others =>
data <= "-------next convBuf <= "--------";
next sampleValid <= '-';
addr <= (others =>
nextwriteAddr <= writeAddr;
nwrite <= '1';
nextresult <= result;
end case;
end process;
process (clk, nextconvBuf)
begin
if(clk'event and clk = '1') then
convBuf <= nextconvBuf;
sampleValid <= next_sampleValid;
writeAddr <= next writeAddr;
result <= nextresult;
end if;
end process;
process (ack, readAddr)
begin
if(ack'event and ack = '1') then
readAddr <= UNSIGNED(readAddr) + 1;
end if;
end process;
output-enable: process(RW, data)
begin
if(RW = '1') then
datapins <= (others => 'Z');
else
datapins <= data;
end if;
end process output_enable;
RW <= nwrite or clk;
nCE <= '0';
--temporary!
nOE <= '0';
overflow <= '0';
newdata <= '0';
end archbigbuf;
88
Appendix A3: ADC Serial Interface Input Control VHDL Source: serin.vhd
--------------
ADC serial to parallel converter, to be used with serout.vhd, which
has the ADC controller. Every two clock cycles, a result that
corresponds to the channel specified by the top three bits of
<counter>, which is bits 4-1 of the global counter, appears at
<result>.
The design depends on the clock being square since the data
is clocked in on the falling edge of the clock. The MAX1281
has a maximum delay of 100 ns between the rising edge of the
clock and data becoming valid; with the minimum cycle time of
208 ns, this leaves 4 ns for the setup time of the registers
at <sin>.
With the serial clock at 4.608 MHz (18.432/4), the
cycle time is 217 ns, making the half cycle 108.5 ns and
leaving 8.5 ns for the register setup time.
library IEEE;
use IEEE.stdlogic_1164.all;
package serinpckg is
component serin is
generic(width: integer :=12);
port (
clk: in STDLOGIC;
counter: in STDLOGICVECTOR(3 downto 0);
sin: in STDLOGICVECTOR(7 downto 0);
result: out STDLOGICVECTOR(width-1 downto 0)
end component;
end serinpckg;
library IEEE;
use IEEE.stdlogic_1164.all;
entity serin is
generic (width: integer := 12);
port (
clk: in STDLOGIC;
counter: in STDLOGICVECTOR(3 downto 0);
sin: in STDLOGICVECTOR(7 downto 0);
result: out STDLOGICVECTOR(width-1 downto 0)
end serin;
architecture archserin of serin is
signal shiftero: STDLOGICVECTOR(width-1 downto 0);
signal shifterl: STDLOGICVECTOR(width-1 downto 0);
signal shifter2: STDLOGICVECTOR(width-1 downto 0);
signal shifter3: STDLOGICVECTOR(width-1 downto 0);
signal shifter4: STDLOGICVECTOR(width-1 downto 0);
signal shifter5: STDLOGICVECTOR(width-1 downto 0);
signal shifter6: STDLOGICVECTOR(width-1 downto 0);
signal shifter7: STDLOGICVECTOR(width-1 downto 0);
signal muxout: STDLOGICVECTOR(width-1 downto 0);
signal latchmux: STDLOGIC;
begin
89
process (clk)
begin
if(clk'event and clk = '0') then
shiftero <= shifter0(width-2 downto
shifteri <= shifterl(width-2 downto
shifter2 <= shifter2(width-2 downto
shifter3 <= shifter3(width-2 downto
shifter4 <= shifter4(width-2 downto
shifter5 <= shifter5(width-2 downto
shifter6 <= shifter6(width-2 downto
shifter7 <= shifter7(width-2 downto
latchmux <= counter(0);
end if;
end process;
process(clk)
begin
if(clk'event and clk = '1')
if(latchmux = '0') then
result <= muxout;
end if;
end if;
end process;
then
with counter(3 downto 1) select
muxout <= shifterO when "000",
shifterl when "001",
shifter2
shifter3
shifter4
shifter5
shifter6
shifter7
when
when
when
when
when
when
"010",
"011",
"100",
"101",
"110",
others;
end archserin;
90
0) & sin(0);
0) & sin(1);
0)
0)
0)
0)
0)
0)
&
&
&
&
&
&
sin(2);
sin(3);
sin(4);
sin(5);
sin(6);
sin(7);
Appendix A4: ADC Serial Interface Output Control VHDL Source: serout.vhd
--------------
module that controls ADCs by serially
sending out control
bytes that are staggered by 2 bits.
<counter> and <addrsel>
should be connected to the lower bits of the global counter
that synchronizes different parts of TEAS; <counter> is bits
4-1 of the global counter, and addrsel is bits 7-5.
the eight serial outputs are in <sout7:0>
The control bytes are sent out at times so that the result
of each channel is available at the same time as when
<counter> reaches that value.
The channel being sampled is incremented by one ahead of
time since the value will not be available for a while.
For example, if <addrsel> is 3, channel 4 is sampled so
that channel 4 data will be available when <addrsel> is 4.
library IEEE;
use IEEE.std logic_1164.all;
use IEEE.stdlogic arith.all;
package seroutpckg is
component serout
port (
clk, rst: in STDLOGIC;
sout: out STDLOGICVECTOR(7 downto 0);
counter: in STDLOGICVECTOR(3 downto 0);
addrsel: in STDLOGICVECTOR(2 downto 0)
end component;
end serout_pckg;
library IEEE;
use IEEE.std logic_1164.all;
use IEEE.std logicarith.all;
entity serout is
port (
clk, rst: in stdlogic;
sout : out STDLOGICVECTOR(7 downto 0);
counter: in STDLOGICVECTOR (3 downto 0);
addrsel: in STDLOGICVECTOR(2 downto 0)
end serout;
architecture archserout of serout is
signal buf: stdlogic vector(22 downto 0);
signal load: std_logic;
signal nextAddr: UNSIGNED (2 downto 0);
begin
process (clk)
begin
if(clk'event and clk = '0') then
if(rst = '1') then
buf <= "000000000000000--------";
elsif(load = '1') then
buf <= buf (21 downto 7) & '1' & STDLOGICVECTOR(nextAddr)
91
& "0111";
else
buf <= buf(21 downto 0) & '0';
end if;
end if;
end process;
-- process that generates one load every sixteen cycles
process (clk)
begin
if(clk'event and clk = '1') then
load <= not counter(3) and counter(2) and counter(1) and counter(0);
end if;
end process;
nextAddr <= UNSIGNED(addrSel) + 1;
sout(0) <= buf(8);
<=
<=
<=
sout(4) <=
sout(5) <=
sout(6) <=
sout(7) <=
sout(l)
sout(2)
sout(3)
buf(10);
buf(12);
buf(14);
buf(16);
buf(18);
buf(20);
buf(22);
end archserout;
92
Appendix A5: Global Counter VHDL Source: cntr.vhd
library IEEE;
use IEEE.stdlogic_1164.all;
use IEEE.stdlogicarith.all;
package cntrpckg is
component cntr
generic (
LENGTH: natural
port
--rst: in STDLOGIC;
in stdlogic;
clk:
cnt: out stdlogicvector(LENGTH-1 downto 0)
end component;
end cntrpckg;
library IEEE;
use IEEE.std logic_1164.all;
use IEEE.stdlogicarith.all;
entity cntr is
generic (
LENGTH: natural:= 32
port
-- rst:
in STDLOGIC;
clk: in stdlogic;
cnt: out stdlogic vector (LENGTH-1 downto 0)
end cntr;
architecture cntr arch of cntr is
signal cntr: std_logic vector(LENGTH-1 downto 0);
begin
count: process(clk)
begin
if(clk'event and clk='l') then
-- if rst='1' then
-- cntr <= TOUNSIGNED(0, LENGTH);
--else
cntr <= UNSIGNED(cntr) + 1;
--end if;
end if;
end process count;
cnt <= cntr;
end cntrarch;
93
Appendix A6: TEAS Integration VHDL Source: teas.vhd
library IEEE;
use IEEE.stdlogic_1164.all;
use IEEE.stdlogic arith.all;
entity TEAS is
port (
-- global pins
rst: in std logic;
clk: in std logic;
-- ADC interface pins
sclk: buffer stdlogic;
sout: out stdlogic vector (7 downto 0);
sin: in std logic_vector(7 downto 0);
-- ringbuf controller pins
ringRW: buffer std logic;
ring nOE, ring_nCE: out std logic;
ring addr: out std logicvector(11 downto 0);
--ring_result: out std_logic vector(ll downto 0);
--ring_resultValid: out std logic;
ring-data: inout stdlogic vector(13 downto 0);
ring uCaddr: in std logicvector(7 downto 0);
ring uCdata: in std logicvector(l1 downto 0);
ring uCwr: in std logic;
ring uCmode: in std logic;
ring bufSize: in stdlogic vector(2 downto 0);
ring loadBufSize: in std_logic;
-- bigbuf pins
fifo RW: buffer std logic;
fifonOE, fifonCE: out std logic;
fifoaddr: out std logic_vector(20 downto 0);
fifodatapins: inout stdlogic vector(7 downto 0);
fifooverflow, fifonewdata: out std logic;
fiforesult: buffer stdlogic vector(7 downto 0);
fifoack: in stdlogic
end TEAS;
architecture TEASarch of TEAS is
constant length: natural := 32;
signal cnt: stdlogicvector(length-1 downto 0);
signal ADCresult: STDLOGICVECTOR(11 downto 0);
signal ringresult: stdlogicvector(11 downto 0);
signal ringresultValid: std logic;
component bigbuf is
generic (
addrlines: integer := 21);
port
(
-- internal connections to other VHDL modules
clk, reset: in std logic;
countl: in stdlogic vector(l downto 0);--two lowest bits of global counter
sample: in stdlogicvector(l1 downto 0);
validIn: in stdlogic;
-- connections to buffer SRAM
RW: buffer stdlogic;
nOE, nCE: out stdlogic;
addr: out std_logicvector(addrlines-1 downto 0);
94
datapins: inout std logicvector(7 downto 0);
-- connections to microcontroller
overflow, newdata : out std logic;
ack: in std logic;
result: buffer std logic_vector(7 downto 0)
end component;
component cntr is
generic (
LENGTH: natural
port
--rst:
in STDLOGIC;
clk: in std logic;
cnt: out stdlogicvector(LENGTH-1 downto 0)
end component;
component ringbuf is
port (
clk, reset: in std logic;
RW: buffer stdlogic;
--
1 = read, 0 = write
nOE, nCE: out stdlogic;
addrh: in stdlogic vector(5 downto 0);--chan. #, bits 7-2 of glob. counter
countl: in stdlogic vector(l downto 0);-- two lowest bits of glob. counter
addr: out stdlogic vector(ll downto 0);
sample: in std_logic vector(11 downto 0);
result: out std logic vector(11 downto 0);
resultValid: out std logic;
-- set to indicate valid result
datapins: inout std logic_vector(13 downto 0);
-- actual I/O pins
time: in stdlogicvector(23 downto 0);
-- upper 24 bits of global counter
-- pins for microcontroller parameter access
uCaddr: in std_logicvector(7 downto 0);
uCdata: in stdlogicvector(ll downto 0);
uCwr: in stdlogic;
uCmode: in stdlogic;
-- pins for setting up number of samples per trigger
bufSizeIn: in stdlogic vector(2 downto 0);
loadBufSize: in std logic
end component;
component serin is
generic(width: integer :=12);
port (
clk: in STDLOGIC;
counter: in STDLOGICVECTOR(3 downto 0);
sin: in STDLOGICVECTOR(7 downto 0);
result: out STDLOGICVECTOR(width-1 downto 0)
end component;
component serout
port (
clk, rst: in STDLOGIC;
sout: out STDLOGICVECTOR(7 downto 0);
counter: in STDLOGICVECTOR(3 downto 0);
addrsel: in STDLOGICVECTOR(2 downto 0)
end component;
95
begin
uO: cntr generic map(LENGTH=>length)
port map(clk=>clk, cnt=>cnt);
ul:
u2:
u3:
ringbuf port map(clk=>clk, reset=>rst, RW=>ringRW, nOE=>ringnOE,
nCE=>ringnCE, addrh=>cnt(7 downto 2),
countl=>cnt(l downto 0), addr=> ring_addr,
sample=>ADCresult, result=>ringresult,
resultValid=>ringresultValid, datapins=>ringdata,
time=>cnt(31 downto 8),
uCaddr=>ring uCaddr, uCdata=>ring_uCdata, uCwr=>ringuCwr,
uCmode=>ring uCmode, bufSizeIn=>ringbufSize,
loadBufSize=>ringloadBufSize);
serout port map(clk=>cnt(0), rst=>rst, sout=>sout,
addrsel=>cnt(7 downto 5),
counter=>cnt(4 downto 1));
serin port map(clk=>cnt(0), sin=>sin, result=>ADCresult,
counter=>cnt(4 downto 1));
u4: bigbuf generic map(addrlines=> 21)
port map (clk=>clk, reset=>rst, RW=>fifoRW, nOE=>fifonOE,
nCE=>fifonCE, addr=>fifoaddr, datapins=>fifodatapins,
validIn=>ringresultValid,
sample=>ring result,
countl=>cnt(l downto 0), result=>fiforesult,
ack=>fifoack, overflow=>fifo overflow,
newdata=>fifo newdata);
sclk <= cnt(0);
end TEASarch;
96
Appendix B: Microcontroller Code to Configure FPGA
This appendix contains the assembly program that runs on the TI MSP430F149.
This program sets up the microcontroller to run off of its internal RC oscillator,
configures the FPGA, and then switches the clock source to an external clock provided
by the configured FPGA. Most of the FPGA configuration data has been omitted since it
is automatically generated by the Java program in Appendix C and since it does not
convey any information about the microcontroller software. As with the VHDL code,
this program is constantly evolving; the following code has been run on the digital
prototype to successfully configure the FPGA.
"msp430xl4x.h"
#include
This program configures the altera flexlOk3Oa fpga serially.
INTERRUPT VECTORS --
--
ORG
DW
;reset vector
OFFFEh
reset
;beginning of flash memory (use
ORG
04000h
mov
mov
#0x0200, SP
#Ox5A8O, &WDTCTL
01100h
for fl49)
reset
;
set
;initialize stack ptr to lowest RAM addr
;turn off watchdog timer
up oscillator
;setupOsc
bis.b
bic
#XTS, &BCSCTL1
#OSCOFF, SR
;enable high frequency for CLK1
;turn on LFXT1 oscillator
#OFIFG,&IFG1
#0x0FFF,r15
;clear OscFault flag
;time to wait
;setupOscl
bic.b
mov
;setupOsc2
dec
jnz
bit.b
jnz
mov.b
;wait...
r15
setupOsc2
;check OscFault flag
#OFIFG,&IFG1
;repeat if necessary
setupOscl
;use CLK1, undivided, everywhere
#11001000b, &BCSCTL2
; set up I/O directions
mov. b #0xFF, &P1DIR
mov. b #0x00, &P1OUT
;set P1 to all outputs
;turn off all pins
------------------------- ~---------------- ~~-;fpgaprog:
~~----- ~---------- --
- - - - -
routine for configuring flex10k30a FPGA.
routine assumes
;This
;interrupts to be off
;Registers
r4,
that the appropriate I/0 lines are configured for
(if applicable).
r5, and r5 are used.
97
All labels are prefixed with FPGAPROG_ or fpgaprog_.
The constants below are organized as pin number, R/W port, direction
; register, function select register.
The R/W ports are identified with an R
; or W after the pin name, direction with D after pin name, and S (for SEL) for
; the function register.
FPGAPROGCLK
FPGAPROGCLKW
FPGAPROGCLKD
FPGAPROGCLKS
EQU
EQU
EQU
EQU
Ox2 0
FPGAPROGDO
FPGAPROGDOW
FPGAPROGDOD
FPGAPROGDOS
EQU
EQU
EQU
EQU
Ox4 0
FPGAPROG_CFG
FPGAPROGCFGW
FPGAPROGCFGD
FPGAPROGCFGS
EQU
EQU
EQU
EQU
PlOUT
PlDIR
PlSEL
FPGAPROGSTAT
FPGAPROGSTATR
FPGAPROGSTATD
FPGAPROGSTATS
EQU
Ox20
FPGAPROGCD
FPGAPROGCDR
FPGAPROGCDD
FPGAPROGCDS
EQU
EQU
EQU
EQU
;synchronous transfer clock
P5OUT
P5DIR
P5SEL
;synchronous data
P50UT
P5DIR
P5SEL
Ox8 0
EQU
EQU
EQU
Ox4 0
PlIN
PlDIR
PlSEL
;nCONFIG, pull down for at least
; 2 us to begin configuration
;nSTATUS, goes low if error
PlIN
PlDIR
PiSEL
;CONF DONE; goes high at end
; of configuration
fpgaprog
;turn off output pins
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGDO, &FPGAPROGDOW
bis.b #FPGAPROGCFG, &FPGAPROGCFGW
;nCONFIG is active low
;set up I/O line directions
bis.b #FPGAPROGCLK,&FPGAPROGCLKD
;CLK is output
bis.b #FPGAPROGDO,&FPGAPROGDOD ;DO is output
bis.b #FPGAPROGCFG,&FPGAPROGCFGD
;nCONFIG is output
bic.b #FPGAPROGSTAT,&FPGAPROGSTATD
;nSTATUS is input
bic.b #FPGAPROGCD,&FPGAPROGCDD ;CONFDONE is input
;set up all I/O pins for regular I/O mode (no peripherals)
bic.b #FPGAPROGCLK,&FPGAPROGCLKS
bic.b #FPGAPROGDO,&FPGAPROGDOS
bic.b #FPGAPROGCFG,&FPGAPROGCFGS
bic.b #FPGAPROG STAT,&FPGAPROG STATS
bic.b #FPGAPROGCD,&FPGAPROGCDS
bis.b
bic.b
#OxO1, &P1OUT
#0xO1, &P1OUT
;squareWave
;pulse nCONFIG low to initiate configuration
bic.b #FPGAPROGCFG, &FPGAPROGCFGW
mov
#0x08,r4
fpgaprogdelayl
dec
r4
jnz
fpgaprogdelayl
bis.b #FPGAPROGCFG, &FPGAPROGCFGW
mov
#0x40,r4
98
(must be at least 2us)
;fpgaprogdelay2
dec
r4
jnz
fpgaprogdelay2
squareWave
jmp
fpgaprogwaitSTAT
bit.b #FPGAPROGSTAT,&FPGAPROGSTATR
jz
fpgaprog-waitSTAT
mov
#PROGFILE, r4
fpgaprogbyteLoop
cmp
#ENDPROGFILE, r4
jeq
fpgaprogafterClocking
mov.b @r4+, r5
;get next byte
cmp
#0, r5
;treat zeros differently for
jeq
fpgaprogsendZeros
compression purposes
mov
#0x08, r6
;use r6 to count bits
fpgaprogbitLoop
bic.b #FPGAPROGDO, &FPGAPROGDOW
bit.b
#OxO1, r5
jz
fpgaprogtoggleClock
bis.b #FPGAPROGDO, &FPGAPROGDOW
fpgaprogtoggleClock
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
r6
dec
fpgaprogbyteLoop
jz
r5
;set up the next bit
rrc
fpgaprogbitLoop
jmp
fpgaprogsendZeros
mov.b @r4+, r5
;next location contains number of
; additional zeros, so add one for total
add.b 41, r5
bic.b #FPGAPROGDO, &FPGAPROGDOW
fpgaprogzeroLoop
;1 (8 clk cycles per zero byte)
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROG CLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
r5
dec
jz
fpgaprogbyteLoop
fpgaprogzeroLoop
jmp
fpgaprogafterClocking
; set up oscillator
setupOsc
bis.b #XTS, &BCSCTL1
#OSCOFF, SR
bic
setupOscl
;enable high frequency for CLK1
;turn on LFXT1 oscillator
99
bic .b
mov
setupOsc2
dec
;clear OscFault flag
;time to wait
#OFIFG,&IFG1
#OxOFFF,r15
mov.b
;wait...
r15
setupOsc2
;check OscFault flag
#OFIFG,&IFG1
;repeat if necessary
setupOsci
;use CLK1, undivided, everywhere
#11001000b, &BCSCTL2
bis.b
jmp
#OxOl, &PlOUT
fpgaprog
jnz
bit.b
jnz
#001h,&PlOUT
xor.b
Mainloop
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
#FPGAPROGCLK, &FPGAPROGCLKW
bic.b
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
#FPGAPROGCLK, &FPGAPROGCLKW
bic.b
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic .b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROGCLKW
bis.b #FPGAPROGCLK, &FPGAPROGCLKW
bic.b #FPGAPROGCLK, &FPGAPROG CLKW
Mainloop
jmp
mov
dec
Ll
jmp
PROGFILE
DB Oxff,
DB Oxff,
Oxff,
DB
DB
Oxff,
Oxff,
DB
Oxff,
DB
DB Oxff,
DB Ox80,
DB OxOC,
DB OxCO,
DB OxCO,
DB Ox18,
DB 0x30,
DB 0x03,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
Ox01,
Ox62,
Ox26,
OxcO, Ox00,
Ox80, Ox01,
OxOC, Ox03,
Ox00, Ox06,
OxOO, Ox00,
Oxf
Oxf
Oxf
Oxf
Oxf
Oxf
f,
f,
f,
f,
f,
f,
Oxff,
Oxf f,
Oxf f,
Oxff,
Oxf f,
Oxf f,
Oxf f,
Ox33,
Oxf f,
Oxf f,
Oxf if,
Oxf f,
Oxf f,
Oxf f,
Ox30, Ox40, Ox06,
Ox03, Ox60, OxOO, OxOC,
OxOc,
OxOO,
OxOO,
Ox60,
Delay to R15
Decrement R15
Delay over?
Again
#065000,R15
R15
Ll
Mainloop
jnz
Toggle P1.0
;l (8 clk cycles per zero byte)
OxOO,
Oxff,
Oxf f,
Oxff,
Oxff,
Oxff,
Oxff,
OxcO,
OxOc,
Ox00,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
Oxf f,
Ox00,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
Oxf f,
OxOO,
OxCO,
Ox80, Ox09,
Ox18, Ox20, Ox03,
Ox04, Ox06, OxcO,
Ox60, OxO 0, OxOO, OxOc,
OxcO, Ox00, OxOO, Ox18,
Ox0c, Ox80, Ox01, Ox30,
OxCO,
OxOO,
Oxf f,
Oxff,
Oxff,
Oxff,
Oxff,
Oxff,
OxOO,
8
18
28
38
48
58
67
76
84
92
103
111
118
126
Oxf f
Oxf f
Oxf f
Oxf f
Oxf f
Oxf f
OxOc
Ox19, Ox00
Ox30, Ox00
Ox60, Ox00
OxOO, Ox00
Ox80, Ox01
Ox00, Ox00
OxOO, Ox00
;<bulk of configuration data omitted>
DB
DB
DB
DB
OxCO,
Oxc8,
0x06,
OxOO,
Ox12, Ox40, Ox02, Ox48,
Oxfc, Ox00,
OxcO, Ox00,
Ox0c, Ox80,
OxOO, OxOO,
OxOC, OxOc, Ox80, Ox01,
Ox00, Ox18, OxOO, OxOO,
OxO 1, Ox30, OxOO, OxCO,
100
Ox09, Ox20,
Ox30, Ox00,
Ox03, Ox60,
Ox06, OxcO,
Ox01
Ox00
Ox00
Ox00
;
;
;
;
50685
50693
50701
50709
DB
DB
DB
DB
DB
DB
OxOO, Ox3O, Oxfd, Oxff,
ENDPROGFILE
END
OxOO, Oxl8, OxOO, OxOO, OxO3, Ox6O,
OxOl, OxOO, OxO4, OxO6, OxcO, OxOO,
OxO3, Ox6O, OxOO, OxOO, OxOc, Ox8O,
OxO6, OxcO, OxOO, OxOO, Oxl8, OxOO,
OxOO, OxOc, Ox8O, OxOl, Ox3O, OxOO,
Oxff
101
OxOO,
OxOO,
OxOl,
OxOO,
OxOO,
OxOO,
Oxl8,
Ox3O,
OxO3,
OxO6,
OxOc,
OxOO,
OxOO,
Ox6O,
OxcO,
Ox8O
OxOO
OxOO
OxOO
OxOO
;
;
;
;
;
50716
50727
50735
50743
50751
Appendix C: Java Source for FPGA Configuration File Compression
The following three files are used to compress the FPGA configuration file. The
output of the Altera compiler is fed to this program, whose output is then pasted in the
microcontroller program's data section. The file I/O code of appendices C2 and C3 are
based on code originally written by Johann Burgert. The three files are:
" Appendix Cl: readbin.java
* Appendix C2: FileIO.java
* Appendix C3: BadFilenameException.java
Appendix Cl: readbin.java
package readbin;
import java.io.*;
public class readbin
static void main(String[] args)
final int
CONFBYTES = 50756;
//final int CONFBYTES = 28941;
String filename = "testfile.ttf";
String result = "";
int vals[] = new int[CONFBYTES];
try (
result = FileIO.readStringFromFile(filename);
FileIO.writeStringToFile(result, "uncompressed.txt");
}
catch(BadFilenameException e)(
System.out.println("bad file name");
}
String
temp
int currentChar = 0;
result = result +
,';
for(int i = 0; i < CONFBYTES; i++){
',')
while(result.charAt(currentChar)
temp += result.charAt(currentChar);
currentChar++;
currentChar++;
vals[il = Integer.parseInt(temp);
//System.out.println (i + "\t0x" + Integer. toHexString (vals[i] ))
temp = "";
//
begin creating result using array of values
StringBuffer s = new StringBuffer();
int linechars = 0;
boolean prevZero = false;
int zeroCount = 0;
for(int i = 0; i < CONFBYTES; i++){
if (vals [i] == 0) {
102
if (prevZero)
zeroCount++;
else{
if(linechars == 0)
s.append("DB
");
else
s.append(", ");
zeroCount = 0;
prevZero = true;
s.append("OxOO");
linechars++;
}
else {
if(linechars
== 0)
s.append("DB ");
else
s.append(", ");
if (prevZero)
i--;
if(zeroCount < 16)
s.append("OxO");
else
s.append("Ox");
s.append(Integer.toHexString(zeroCount));
prevZero = false;
else{
if(vals[i] < 16)
s.append("OxO");
else
s.append("Ox");
s.append(Integer.toHexString(vals[i]));
linechars++;
if(linechars
s.append("
linechars
==
=
10){
; " + i + "\r\n");
0;
}
result = s.toString(;
try (
FileIO.writeStringToFile(result, "result.txt");
}
catch(BadFilenameException e)
System.out.println("bad file name");
103
Appendix C2: FileIO.java
package readbin;
import java.io.*;
public class FileIO
{
public static String readStringFromFile(String filename) throws
BadFilenameException {
/* effects: returns the contents of the file named
by <filename>, unless:
*
*
an I/O error occurs in the process of opening,
*
reading, and closing the file named by <filename>
*
=> BadFilenameException
//test if args are defined:
if(filename == null) {
throw new BadFilenameException("<filename>
FileIO,readStringFromFile");
is null in
int fileItem;
StringBuffer tempString = new StringBuffer(;
// A single try block is sufficent because the catch prints the
// specific message from the IOexception which defines
// any write problem
try {
//using BufferedReader for speed
BufferedReader input = new BufferedReader(new
FileReader(filename));
int count = 0;
while ((fileItem = input.read()) != -1)
//tempString.append((char) fileItem);
//tempString.append(fileItem + "
");
if(!Character.isWhitespace((char) fileItem))
tempString.append((char) fileItem);
input.close();
catch(IOException fileError)
throw new BadFilenameException("IOexception while reading file:
in FileIO.readStringFromFile().\n Message: " +
filename + "\n
fileError.getMessage();
"
+
return tempString.toString();
public static void writeStringToFile(String str, String filename) throws
BadFilenameException (
/* effects: creates a new file named by <filename>
whose contents are the contents of <str>, unless:
*
*
a file named by <filename> already exists
*
=> BadFilenameException
an I/O error occurs in the process of creating,
*
writing, and closing the file named by <filename>
*
104
=> BadFilenameException
*
//test if args are defined:
if (filename == null) (
throw new BadFilenameException("<filename>
FileIO.writeStringToFile");
is null in
}
(str == null)
throw new BadFilenameException("<str> is null in
FileIO.writeStringToFile");
if
}
int
i, stringLength=str.length();
A single try block is sufficent because the catch prints the
specific message from the IOexception which defines
// any write problem
try {
//
//
//
//
only creates a file object that can then see if it is legal
by checking for the existence of a file of the same name
File outFile = new File(filename);
//
//
if tests to insure that outFile does not exist
=> throws BadFilenameException
//removed to implement change in spec->clobbers existing files
//if (outFile.createNewFile() {
//use a BufferedWriter for speed
BufferedWriter output = new BufferedWriter(new FileWriter(outFile));
for (i = 0; i < stringLength; i++) {
output.write((int) str.charAt(i));
output.close();
//want
to clobber files
else
throw new BadFilenameException("Attempt to write to File which already
exists" + "\n
in FileIO.writeStringToFile()");
catch(IOException fileError)
throw new BadFilenameException("IOexception while writing
filename + "\n in FileIO.writeStringToFile() .\n
Message: " +
fileError.getMessage());
105
file:
" +
Appendix C3: BadFilenameException.java
package readbin;
*
readbin.BadFilenameException.java
******************
*****
*
*****/
public class BadFilenameException extends Exception
public BadFilenameException() {)
public BadFilenameException(String msg)
super (msg);
106
Appendix Dl: BGA ZIF Socket Pinout
The irregular and undocumented pinout of the Emulation Technology, Inc. ZIF socket
took substantial time to determine. The pinout is valid for a top view, with the release
lever on the right side, as shown in the picture of the digital prototype in Figure 36.
Jl
H
K'>
(E"
1G
F)jj
(M3
N2)
K3
(P
P2
L3
Ri
J5)
J6
( K5
K8)
K9
N
T2 )
4
E3
F3
C 3
D3)
1
G5
F5
E4( E5
F4
D4
G
(E6
F")
H(
F7 )
E7)
( E8 \)
G6)
H7
'
C4)
C5)
IC6)
F6
G7)
D6
D7(
DS)
7)
I"
A4)
( " )A ES6)
A2
J)i;G1'
(,Fa ""
B3 )
B5
(B4
K6
L5 I
K7
L8
L7
L6
M6)
P2 P3)
4
C
D 1)
C
HB
IB0
B1 11
(
(Dl)
(A
Dl
Dl
C1 l
R5
R
P5
P6)
PR)
T6
J8
A
"~
("A
Al I
(815
B14)
MS
N4)
N5
Eli1)
(F19
CG)
(F9~
EG I
E
E
F
N)
I
N9)
(N1
P9)
'E9
G)
(D
F1
HI)
R8
JC5H
(""7
All)
Al
)3) F
T4
A9,
(87)
08C9
D9)
A8)
( B6)
C)
B9
H2
( A6)
A2'~ A3
l
Cl,'
K4
L4
3)
G3
A
HCH
(B2)
(C2
,4 )H4)
N3
T1
(H3)
J3
(M3)
M7
M
(H
K2 )
M2
M
(B
(D2)
F2') E2)
(2
'Li)
"D CD )
Nll
N10
Nl
M12
L11)
( KI
13
Ml
)
(K3
J 31
C
C
F A'
(
HH
D(/
D
1
E16
Rid
18
19T
P1
R 1
T112
R13)
CT"-2'
Tii'
(14)
(P12
M 10
1
T"' 5 115 /NJ~1,t
Hl
P14
L l?)
KM1) (K
P 3
R (R
)
(J-12)
/'"I
(1)
"""\
Ni4
M 1\
P
,
Pl
N-"
(P16i
( L 14)
J14)
J)
Gi
Q
K
(N
K"'
Figure 40: BGA ZIF socket pinout.
107
K1
Ml
(""
1L6'
K1
Ji N
H14
""