April 08, 2008
Lev Uvarov
CSR_SCC – SP Core Configuration
This read/write register keeps the SP core configuration options. The register is protected
against accidental accesses: in order to get VME access to this register the SP should be set to the
VME fast control mode.
Please note that the register format has slightly changed: DTE bit has moved from D8 to
D7 to free up space for Pre-Trigger control setting. Also, the BXA control has increased by 1
BX. Core Version bits are read-only bits.
Table 1: CSR_SCC Data Format for SP_FPGA (SP Core Version 0)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
0
0
Core Version
D9
X
0
D8
DTE
DTE
D7
D6
X
X
0
0
Mode Control
D5
D4
Q4EN Q3EN
Q4EN Q3EN
D3
D2
D1
D0
X
X
X
BXE
0
0
0
BXE
Bunch Crossing Analyzer
TRN
WR
RD
Here:
− X – Don’t care bit for writes and zero for reads;
− BXE = 0 (default) / 1 – disable (default) / enable Bunch Crossing Analyzer;
− DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
− Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
− Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4.
Table 2: CSR_SCC Data Format for SP_FPGA (SP Core Versions 1)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
0
1
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
X
Q4EN Q3EN
0
Q4EN Q3EN
Mode Control
D3
D2
D1
D0
X
X
BXA1 BXA0
0
0
BXA1 BXA0
Bunch Crossing Analyzer
TRN
WR
RD
Here:
− X – Don’t care bit for writes and zero for reads;
− PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
− DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
− Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
− Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4;
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
DAT_ETA – Eta Min/Max/Win Data
This read/write register provides access to the Eta register file content. The register file
keeps data for Eta Minimum – 8 words, Eta Maximum – 8 words, Eta Window – 6 words and
Eta Offset – 4 words setting, in that order, which totals to 26 data words. The CNT_ETA counter
provides indexed access to the register content; see the CNT_ETA register description for
details.
There are 8 types of pair-wise extrapolations between 2 stations in the core SP logic,
which listed in numerical order are:
1. ME1-ME2
2. ME1-ME3
3. ME2-ME3
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April 08, 2008
Lev Uvarov
4. ME2-ME4
5. ME3-ME4
6. ME1-ME2ov
7. ME2-MB1
8. ME2-MB2.
The last type is no longer implemented in hardware (the SP doesn't get the signals) but
still exists in the firmware input. In the extrapolation unit the requirement is that Eta from each
track segment lie in this range. There is also a cut on the difference in Eta, called Eta Window,
between two stations for the first 6 CSC extrapolation units, since the DT system does not sent
Eta values. This cut is very powerful against beam halo muons. Eta Offsets can be added to each
CSC station (ME1-4) to compensate for chamber offsets in beam test data.
This register is protected against accidental accesses: in order to get VME access to this
register the SP should be set to the VME fast control mode.
Table 3: DAT_ETA Data Format for SP_FPGA (SP Core Version 0)
D15
X
0
D14
X
0
D13
X
0
D12
X
0
D11
D10
X
X
0
0
Not Used
D9
X
0
D8
X
0
D7
X
0
D6
D5
D4
D3
D2
D1
D0
TRN
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0 WR
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0 RD
EtaMinimum Parameters, 8 each
X
0
X
0
X
0
X
0
X
0
Not Used
X
0
X
0
X
0
X
0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
EtaMaximum Parameters, 8 each
WR
RD
X
0
X
0
X
0
X
X
0
0
Not Used
X
0
X
0
X
0
ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
EtaWindow Parameters, 6 each
WR
RD
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Not Used
X
0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
EtaOffset Parameters, 4 each
WR
RD
Here:
− X – don’t care bit;
− ETAP [6:0] = 0…127 (default = 22, 22, 14, 14, 14, 10, 10, 10) eight values for Eta
Minimum parameters;
− ETAP [6:0] = 0…127 (default = 127, 127, 127, 127, 127, 24, 24, 24) eight values for
EtaMaximum parameters;
− ETAP [7:0] = 0…255 (default = 2, 2, 2, 2, 2, 2) six values for EtaWindow
parameters;
− ETAP [6:0] = 0…127 (default = 0, 0, 0, 0) four values for EtaOffset parameters;
For the “SP Core Version 1” four EtaOffset parameters are replaced with the MindPhi,
MindEta_Acc, MaxdEta_Acc and MaxdPhi_Acc parameters.
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April 08, 2008
Lev Uvarov
Table 4: DAT_ETA Data Format for SP_FPGA (SP Core Version 1)
D15
X
0
D14
X
0
D13
X
0
D12
X
0
D11
D10
X
X
0
0
Not Used
D9
X
0
D8
X
0
D7
X
0
D6
D5
D4
D3
D2
D1
D0
TRN
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0 WR
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0 RD
EtaMinimum Parameters, 8 each
X
0
X
0
X
0
X
0
X
0
Not Used
X
0
X
0
X
0
X
0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
EtaMaximum Parameters, 8 each
WR
RD
X
0
X
0
X
0
X
X
0
0
Not Used
X
0
X
0
X
0
ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
EtaWindow Parameters, 6 each
WR
RD
X
0
X
0
X
0
X
0
X
X
0
0
Not Used
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Not Used
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Not Used
X
0
X
0
X
0
X
0
X
0
X
X
0
0
Not Used
X
0
X
0
X
0
ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
MindPhi Parameter
WR
RD
X
0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
MindEta_Acc Parameter
WR
RD
X
0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
MaxdEta_Acc Parameter
WR
RD
ETAP9 ETAP8 ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
ETAP9 ETAP8 ETAP7 ETAP6 ETAP5 ETAP4 ETAP3 ETAP2 ETAP1 ETAP0
MaxdPhi_Acc Parameter
WR
RD
Here:
− X – don’t care bit, reads back as zero;
− ETAP [6:0] = 0…127 (default = 22, 22, 14, 14, 14, 10, 10, 10) eight values for Eta
Minimum parameters;
− ETAP [6:0] = 0…127 (default = 127, 127, 127, 127, 127, 24, 24, 24) eight values for
EtaMaximum parameters;
− ETAP [7:0] = 0…255 (default = 2, 2, 2, 2, 2, 2) six values for EtaWindow
parameters;
− ETAP [5:0] = 0…63 (default = 2) MindPhi - Minimum phi difference for track
cancellation logic;
− ETAP [6:0] = 0…127 (default = 4) MindEta_Acc - Minimum Eta difference for
accelerator tracks;
− ETAP [6:0] = 0…127 (default = 16) MaxdEta_Acc - Maximum Eta difference for
accelerator tracks;
− ETAP [9:0] = 0…1023 (default = 64) MaxdPhi_Acc - Maximum Phi difference for
accelerator tracks.
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