Track-Finder Test Results and VME Backplane R&D D.Acosta University of Florida
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Track-Finder Test Results and VME Backplane R&D D.Acosta University of Florida EMU Meeting, FNAL, December 2000 1 Darin Acosta Technical Design Report èTrigger TDR is completed! èA large amount effort went not only into the 630 pages, but into CSC Track-Finder prototypes, tests, and simulations èLatest test results and R&D reported in this talk èSimulation results reported in software session EMU Meeting, FNAL, December 2000 2 Darin Acosta Level-1 Trigger Architecture From DT Track-Finder (Vienna) 12 Sector Processors MB1 DT TF 1 Muon Sorter SP ME4 OPTICAL (Vienna) ME2-ME3 To Global Muon Trigger ME1 SR Muon Port Cards PC 3µ / port card (Rice) MS SP 36 Sector Receivers 3µ / sector (UCLA) (Florida) 12 sectors 4µ (Rice) GMT 4µ From DT 8µ Track-Finder RPC EMU Meeting, FNAL, December 2000 3 Darin Acosta Tests of Current Prototypes Prototypes of all Track-Finder components (except the CSC Muon Sorter) have been constructed: è è è è è Sector Processor: Sector Receiver: Muon Port Card: Clock and Control Board: Channel-Link backplane: UFlorida UCLA Rice Rice UFlorida All boards were completed in July Since the last CMS week and EMU meeting, we have focused on completing integration tests of the complete system EMU Meeting, FNAL, December 2000 4 Darin Acosta Track-Finder Crate Tests SP SR CCB MPC Bit3 VME Interface Custom backplane EMU Meeting, FNAL, December 2000 100m optical fibers 5 Darin Acosta Test Results: Sector Processor VME Interface All LUTs and FPGA programs downloaded in less than 30s through SBS Bit3 PCI to VME interface è JTAG serialized on board @ 25 MHz è Functionality Internal dynamic test @ 40 MHz works with 100% agreement with ORCA simulation p 180K single muons (and 60K triple muons) p Internal FIFOs are 256 b.x. deep è Latency is 15 b.x. (not including Channel-Link input) è Firmware updated to latest algorithms for Trigger TDR p Some subtle logic errors discovered and fixed in HW è Plan to test even larger data samples (and random data) to look for any rare errors è EMU Meeting, FNAL, December 2000 6 Darin Acosta Test Results: Sector Receiver Functionality Three boards built and tested è Internal dynamic test @ 40 MHz works with ORCA data and pseudo-random data p Tested 30K cycles of 256 random events è Some rare (10-6) errors encountered and under study è One board with slower SRAM (10ns vs. 8ns) works fine even with 2 memories cascaded with 25 ns clock è Emulation software is similar to ORCA, but not same code p Although LUT contents were generated from ORCA è EMU Meeting, FNAL, December 2000 7 Darin Acosta System Tests Done in Last Month Port Card → Sector Receiver MPC and SR communicate via HP GLinks and optical fiber è Data successfully sent from input of one MPC, through 100m of optical cables, to output of SR è 1.6M random events processed with no errors è Sector Receiver → Sector Processor SR and SP communicate via Channel-Link backplane è Data successfully sent from input of one SR, through custom backplane, into the SP p Some errors encountered from unmasked inputs, but tracks were reconstructed correctly from the SR input è Successfully sent data from three SRs connected to the SP to emulate an entire trigger sector è EMU Meeting, FNAL, December 2000 8 Darin Acosta System Tests (Continued) Port Card → Sector Receiver → Sector Processor Successfully sent data from the input of two MPCs (representing ME2 and ME3), through one SR, and reconstructed tracks correctly in the SP è Complete chain test è The Clock and Control Board prototype coordinated these tests: è è Distributed clock and control signals with programmable delays Sent BC0 to initiate tests Lots of software had to be developed (and coordinated between institutes) for these tests to happen EMU Meeting, FNAL, December 2000 9 Darin Acosta Future Plans: Backplane We plan to replace Channel-Link transmission as much as possible from the CSC trigger path because of its long latency (~3.5 b.x.) In particular, for the custom point-to-point backplane in the Track-Finder crate and the front-end peripheral crates è Florida proposal is to use GTLP at 80 MHz è è è è Doubled frequency achieves 2× signal reduction (vs. 3× from Channel-Link) Can be bussed (although we plan point-to-point) No differential signals (fewer traces) Can be driven by Xilinx Virtex I/O directly, or from driver chips by Fairchild and TI Prototype backplane successfully tested in Florida EMU Meeting, FNAL, December 2000 10 Darin Acosta GTLP Test Fixture Clock generator (160 MHz) Pattern generator Virtex, or Fairchild GTLP16612 GTLP transmitter Backplane connector Shift register Comparator AMP Z-pack 2-mm 5-row GTLP receiver 50 Ω Backplane traces (~220 mm) Error counter and display EMU Meeting, FNAL, December 2000 11 Darin Acosta GTLP Backplane Tests Alternating and random patterns driven up to 160 MHz with no errors Virtex Drivers Backplane traces 80 MHz signal EMU Meeting, FNAL, December 2000 12 Darin Acosta 160 MHz signal Conclusions GTLP backplane technology works well, ready for peripheral crate design Prototype tests were a success (but a lot of work) It was a useful exercise to commission a crate of trigger electronics Validates the trigger architecture è Gives us some idea of what to expect when we commission the real system è Learned of some (solvable) incompatibilities p Different VME addressing conventions p Different patterns and sorting logic than expected è Provides guidance on how to improve future boards p Additional VME registers to set board functions or to spy on intermediate data p A real DAQ readout path for continuous running (i.e. circular buffer with DDU connection) è l In particular, can the TF trigger data “piggy-back” on EMU data? EMU Meeting, FNAL, December 2000 13 Darin Acosta
