Architecture of the 680XX
• Outline
–
–
–
–
680XX Family
68000/68040 Programming Model
68040 Internal Organization
68040 Instruction Pipeline
• Goal
– Understand 680XX programming model
– Understand 68040 organization
• Reading
– Microprocessor Systems Design, Clements,
Ch. 2.1-2.3, 7.5, 7.6
680XX Family
• 68000
–
–
–
–
–
16-bit internal buses
16-bit external buses
some 32-bit instructions
no cache, external MMU
floating-point coprocessor
• 68010
– handle bus error (page fault)
• 68020
– 32-bit buses, execution units
– on-chip instruction cache
– more instruction pipelining
• 68030
– on-chip data cache
– on-chip MMU
– more pipelining
• 68040
– bigger caches
– on-chip floating-point
– deeper pipeline
• 68060
–
–
–
–
–
bigger caches
RISC-like
superscalar
branch prediction
ColdFire is simplified version
680XX Programming Model
• Internal programmer storage
– data registers
– address registers
– special-purpose registers
ColdFire Registers
ColdFire User Registers
Data Registers
• Names - D0 to D7
• Size - 32-bits (longword)
– 16-bit (word) and 8-bit (byte) subsets
• Used for most data manipulation
• General-purpose - any data operation on any data
register
• Operate on longwords, words, and bytes
– Depends on instruction
• Mnemonics - .L, .W, .B suffixes
• Examples
– ADD.L D0,D1 - D1 = D0 + D1 using all 32 register bits
– ADD.B D0,D1 - D1 = D0 + D1 using least significant 8 bits
• More significant register bits unaffected by byte
and word ops
Address Registers
• Names - A0 to A7
• Size - 32-bits
• Pointer registers - contain addresses of data in
memory
– most memory references via address registers
• General-purpose - perform same operations on all
– operations affect all 32 bits
• A7 - stack pointer for subroutine return address
– two A7 registers - for user (USP) and supervisor (SSP) modes
» supervisor mode for operating system
– 68040 - interrupt stack pointer (ISP), master stack pointer
(MSP)
• Off-chip address size
– 24-bits in 68000, 32-bits in 68040
Special-Purpose Registers
• Program counter (PC)
– 32-bits
– address of next instruction to execute
• Status register (SR)
– system/status byte
– condition code register (CCR)
• System/status byte
– controls operating mode
– S - user/supervisor mode
– T - trace mode
» trace exception after each instruction
– I0-I2 - interrupt mask
» current level of interrupt that interrupts
Special-Purpose Registers
• Condition code register (CCR)
–
–
–
–
–
–
–
results of a previous instruction (e.g. ADD)
use to execute conditional operations (e.g. IF)
C - carry bit (for B, W, L operations)
V - overflow (result overflowed)
Z - zero (result is zero)
N - negative (result is negative)
X - extend (carry bit extended to higher bits)
Privileged States
• User mode
– state where user programs execute
• Supervisor mode
– state where operating system executes
• Exceptions and interrupts switch to supervisor
– user does not directly handle them
• Hard reset switches to supervisor
• Privileged instructions
– only execute during supervisor mode
– supervisor can read/write SSP, ISP, MSP, status byte
Memory Organization
• Alignment of bytes, words, longwords in memory
– 680XX is a “big endian” machine
– MSB is stored lowest address location
ColdFire Internal Organization
• Data path
– I fetch, decode, address, D fetch execute, write pipeline
•
•
•
•
•
Instruction cache
Memory management unit
SRAM
Bus interface
Peripherals
ColdFire Core Pipeline