Budapest University of Technology and Economics
Department of Electron Devices
Microelectronics, BSc course
MOS circuits: basic
construction principles
http://www.eet.bme.hu/~poppe/miel/en/15-MOS-circ.ppt
http://www.eet.bme.hu
Budapest University of Technology and Economics
Department of Electron Devices
The abstraction level of our study:
SYSTEM
MODULE
+
GATE
CIRCUIT
Vin
Vout
DEVICE
G
S
n+
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
D
n+
2
Budapest University of Technology and Economics
Department of Electron Devices
Recall: CMOS gates
►
►
►
nMOS network: pulls down the output to GND: Pull-Down
Network (PDN)
pMOS network: pulls up the output to VDD: Pull-Up
Network (PUN)
PUN and PDN are dual networks (duality both in terms of
VDD
graph topology and elements)
VDD
In1
In2
VDD
B
PUN
InN
Y
F(In1,In2,…InN)
A
Y
A
B
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In1
In2
InN
MOS circuits © András Poppe, BME-EET 2008-2014
PDN
3
Budapest University of Technology and Economics
Department of Electron Devices
Complex gate – still "simple":
A
C
B
D
X
D
X = !((A+B)•(C+D))
C
D
A
B
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C
VDD
X
B
A
B
C
D
MOS circuits © András Poppe, BME-EET 2008-2014
PUN
A
GND
PDN
4
Budapest University of Technology and Economics
Department of Electron Devices
Creating dual networks
A
C
A
E
B
19-11-2014
C
E
D
MOS circuits © András Poppe, BME-EET 2008-2014
B
D
5
Budapest University of Technology and Economics
Department of Electron Devices
Dynamic MOS logic
►
Principle: 2 phase operation
 a switching pMOS transistor charges a capacitor to the VDD voltage:
pre-charge phase
 in the next phase the capacitor is disconnected from VDD and it is
discharged or is left intact through an nMOS logic circuit (according to
the logic function realized by this PDN): this is the evaluation phase
Φ
pre-charge
Mp
Out
In1
In2
In3
Φ
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Φ
CL
PDN
evaluation
Me
t
MOS circuits © András Poppe, BME-EET 2008-2014
6
Budapest University of Technology and Economics
Department of Electron Devices
Dynamic gates
Φ
Φ
Mp
Mp
Out
In1
In2
In3
Φ
CL
PDN
Out
A
C
B
Me
Φ
Me
Two phase operation:
Precharge (Φ = 0)
Evaluate (Φ = 1)
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
7
Budapest University of Technology and Economics
Department of Electron Devices
Dynamic gates
Φ
Φ
Mp
off
Mp on
Out
In1
In2
In3
Φ
CL
A
PDN
C
B
Me
Φ
Two phase operation:
Precharge (Φ = 0)
Evaluate (Φ = 1)
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1
Out
!((A&B)|C)
off
Me on
If the output of a dynamic gate is
discharged, it can not be discharged
again until charged up in a pre-charge
phase
MOS circuits © András Poppe, BME-EET 2008-2014
8
Budapest University of Technology and Economics
Department of Electron Devices
Major properties of dynamic gates
► The
logic function is realized by the PDN
 instead of 2N transistors only N+2 transistors are needed
 smaller area than in in case of static CMOS
► Geometrical
ratios do not play important role in the
operation
► There is only dynamic power consumption
► A pre-charge clock signal is needed
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
9
Budapest University of Technology and Economics
Department of Electron Devices
Dynamic operation
CLK
Out
2.5
Evaluate
In1
In2
1.5
In3
In &
CLK
0.5
In4
CLK
Precharge
-0.5
0
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Out
MOS circuits © András Poppe, BME-EET 2008-2014
0.5
Time, ns
1
10
Budapest University of Technology and Economics
Department of Electron Devices
Application of transmission gates
► The
full adder realized by conventional static CMOS
technique is too complex, requires too many
transistors.
► Simplification: application of transmission gates
► Logic function is created not only by switching in the
VDD-GND conduction path
 switch inserted anywhere in a signal path
 analog switch in a digital circuit
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
11
Budapest University of Technology and Economics
Department of Electron Devices
Logic with transmission gates
► In
CMOS: n/p transistors with inverted control (gate)
voltages
Transmission gate with
inverted control
Transmission gate with builtin inverter
► less
transistors are needed
► reversible signal path
► no static power consumption
► limitation: insertion resistance – do not use more
than 4 transmission gates in a signal path
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
12
Budapest University of Technology and Economics
Department of Electron Devices
Static CMOS full adder
!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)
!Cout = !Cin & (!A | !B) | (!A & !B)
B
A
B
B
A
Cin
A
B
Cin
Cin
!Cout
!Sum
A
B
A
B
A
Cin
A
B
Cin
A
B
Cout = Cin & (A | B) | (A & B)
19-11-2014
Sum = !Cout & (A | B | Cin) | (A & B & Cin)
MOS circuits © András Poppe, BME-EET 2008-2014
13
Budapest University of Technology and Economics
Department of Electron Devices
Examples with transmission gates
► Typical:
XOR, mux/demux
 XOR gate:
B
Y = A XOR B
A
 4 input MUX:
NS0
S0
NS1
D0
NS0
S1
NS1
D3
S0
S1
D1
S1
D2
D1
NS0
S0
S1
NS1
Y
D2
NS0
NS1
D0
Y
NS1
D3
S0
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S1
MOS circuits © András Poppe, BME-EET 2008-2014
14
Budapest University of Technology and Economics
Department of Electron Devices
Full adders with TG-s
Cin
B
A
Sum
16 tr.
Cout
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MOS circuits © András Poppe, BME-EET 2008-2014
16
Budapest University of Technology and Economics
Department of Electron Devices
Static CMOS full adder
!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)
!Cout = !Cin & (!A | !B) | (!A & !B)
B
A
B
B
A
Cin
A
B
Cin
Cin
!Cout
!Sum
A
B
A
B
A
Cin
A
B
Cin
A
24 tr.
B
Cout = Cin & (A | B) | (A & B)
19-11-2014
Sum = !Cout & (A | B | Cin) | (A & B & Cin)
MOS circuits © András Poppe, BME-EET 2008-2014
17
Budapest University of Technology and Economics
Department of Electron Devices
Storage circuits: dynamic D ff
► Dynamic
latch & ff
 "Analog SH" circuits in a digital environment
 Storage capacitor: input capacitance of the inverter
D
/Q
EN
CIN
 Two latches in series, controlled by non-overlapping
signals: master-slave FF
CK
CK1
D
2
Q
CK2
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CK1
MOS circuits © András Poppe, BME-EET 2008-2014
18
Budapest University of Technology and Economics
Department of Electron Devices
Storage circuits: dynamic D ff
► Simplified
version:
 No need for a second, non-overlapping CLK
 transmission gate with inverted control
CLK
D
/CLK
Q
CLK
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
19
Budapest University of Technology and Economics
Department of Electron Devices
Static latches and ff-s
► Can
be constructed from logic gates with feedback
loops
/S
/R
Q
D
Q
/Q
/Q
EN
RS-latch
Extended: D-latch
D-latch
5 cells, 18 transistors
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
20
Budapest University of Technology and Economics
Department of Electron Devices
D latch
► with
OR-AND-INVERT gate:
D
Q
Q
/Q
/Q
/EN
D
/EN
/D
The dynamic version took less
space/transistors
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
21
Budapest University of Technology and Economics
Department of Electron Devices
D flip-flop
► two
D latches in series with inverted clock signal
D
Q
QN
Q
D
/Q
CLK
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
22
Budapest University of Technology and Economics
Department of Electron Devices
Memories – hierarchy
On-Chip Components
Control
eDRAM
Instr Data
Cache Cache
.1’s
1’s
10’s
100’s
Size (bytes):
100’s
K’s
10K’s
M’s
Cost:
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ITLB DTLB
Speed (ns):
Datapath
RegFile
Second
Level
Cache
(SRAM)
highest
MOS circuits © András Poppe, BME-EET 2008-2014
Main
Memory
(DRAM)
Secondary
Memory
(Disk)
1,000’s
T’s
lowest
23
Budapest University of Technology and Economics
Department of Electron Devices
Semiconductor memories
RWM
NVRWM
ROM
EPROM
Maskprogrammed
Random
Access
SRAM
(cache,
register
file)
Non-Random
Access
FIFO/LIFO
E2PROM
DRAM
Shift Register
FLASH
CAM
Electricallyprogrammed
(PROM)
See the structures later
19-11-2014
MOS circuits © András Poppe, BME-EET 2008-2014
24
Budapest University of Technology and Economics
Department of Electron Devices
Development of DRAMs
1000000
256 000
100000
Kbit capacity
64 000
16 000
10000
4 000
1000
1 000
256
100
64
See the structures later
10
1980
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
Year of introduction
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MOS circuits © András Poppe, BME-EET 2008-2014
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