Massachusetts Institute of Technology
Kavli Institute for Astrophysics and Space
Research (MKI)
FPE Firmware Design Specification
Dwg. No. 37-14011
Revision C
Date 6/15/2015
37-32002
Page 1 of 34
Revision C
Table of Contents
1
PREFACE
1.1
1.2
1.3
5
REVISIONS
REFERENCES
OPEN QUESTIONS
5
5
6
2
SCOPE
6
3
FPE FIRMWARE DESIGN
8
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
4
OVERVIEW
CCD CONTROL
PIXEL TRANSFER
DHU INTERFACES
DATA DOWNLINK (DDL)
SERIAL SYNCHRONOUS BUS FOR COMMAND
FPE HOUSEKEEPING
8
8
9
9
9
9
9
INTERFACES
10
4.1 EXTERNAL INTERFACES DIAGRAM
4.2 INTERFACE DESCRIPTIONS
4.3 CMD BUS
4.3.1 CMD PACKETS
4.3.1.1 Command Packet Format
4.4 DATA DOWNLINK (DDL)
4.4.1 OVERVIEW
4.4.2 TIMING
4.4.3 PACKETS
4.4.3.1 Pixel Packets
4.4.3.2 Housekeeping Packets
4.4.3.3 Requested Memory Packets
4.4.3.4 Primary Control Byte (For Synchronization, Pixel, Housekeeping, and Memory)
4.4.3.5 Secondary Control Byte (For Memory)
4.4.3.6 Status Byte 1
4.4.3.7 Status Byte 2
4.4.3.8 Order of Pixel Packet Transfer (lineA/line B)
4.4.3.9 Order of HSK Packet Transfer
4.4.3.10 Order of Memory Packet Transfer
4.5 CCD DATA INPUT
4.5.1 OVERVIEW
4.5.2 FOCAL PLANE CCD CONNECTIONS
4.5.3 FOCAL PLANE CCD TIMING
4.6 CCD CLOCKS
4.6.1 CONFIGURATION
4.7 HOUSEKEEPING
4.7.1 OVERVIEW
4.7.2 INTERFACE SIGNALS
4.7.3 CONFIGURATION
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10
10
10
10
11
12
12
12
13
13
13
13
13
14
14
15
15
16
16
16
16
17
17
17
17
18
18
19
19
4.8 VOLTAGE CONTROL
4.9 JTAG/DEBUG
4.10 OSCILLATOR CLOCK
4.11 CHIP I/O
5
20
20
20
20
MEMORIES
22
5.1 MEMORY OVERVIEW
5.2 MEMORY DESCRIPTIONS
5.2.1 PROGRAM MEMORY
5.2.2 SEQUENCE MEMORY
5.2.3 HOUSEKEEPING MEMORY
5.2.4 VOLTAGE CONTROL MEMORY
5.2.4.1 Software Programming of Clock Level Voltage Memory
5.2.4.2 Firmware Execution of DAC writes
6
REGISTERS
22
22
22
23
24
24
25
25
26
6.1 REGISTER WRITES
6.2 REGISTER READS
6.3 REGISTER ADDRESS MAP
6.4 REGISTER DESCRIPTIONS
6.4.1 PRG_FS_PTR
6.4.2 HSK_TIME_CONV
6.4.3 HSK_TIME_BTN_SAMPLES
6.4.4 HSK_TOTAL_SAMPLES
6.4.5 HSK_SAMPLES_PER_FRAME
6.4.6 CHARGE_PUMP_ENA
6.4.7 FORCE_STATUS
6.4.8 FRAMES_XMT
6.4.9 TEST_MODE
6.4.10 HSK_SBIT_ERR_CNT
6.4.11 SEQ_SBIT_ERR_CNT
6.4.12 CMD_SBIT_ERR_CNT
7
7.1
7.2
7.3
8
8.1
9
9.1
26
26
26
26
26
27
27
27
27
27
27
28
28
29
29
29
RESETS
29
POWER UP
RESET
FRAME START
29
30
30
CLOCKS
30
CLOCK TREE
30
FPGA CONFIGURATION
31
TYPICAL CONFIGURATION PROCEDURE
31
10 CONVENTIONS
31
11 RADIATION MITIGATION
31
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11.1 CONFIGURATION MEMORY
11.2 ON-CHIP BLOCK RAM
11.3 DESIGN LOGIC
11.3.1 REGISTERS
11.3.2 LOGIC UPSET DETECTION
11.3.2.1 Loss of sync/bad downlink control byte
11.3.2.2 Frame start/Frame end does not occur when expected
11.3.2.3 Commands
11.3.3 LOGIC UPSET MITIGATION
12 DESIGN FOR TEST (DFT)
12.1
12.2
32
32
32
32
32
32
32
33
33
33
DEBUG I/O
IMAGE GENERATION
33
33
13 CURRENT POWER ESTIMATES
33
14 ACRONYMS/ABBREVIATIONS
34
Tables in Document
Table 1: List of Memories ................................................................................................................................ 22
Table 2: Register Address Map ..................................................................................................................... 26
Table 3: Clocks ..................................................................................................................................................... 30
Table 4: Acronyms/Abbrevations................................................................................................................ 34
Figures in Document
Figure 1: FPE/DHU Overview ........................................................................................................................... 7
Figure 2: Block Diagram ..................................................................................................................................... 8
Figure 3: External Interfaces.......................................................................................................................... 10
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Revision C
1
Preface
1.1
Revisions
Rev.
01q
Aq
1.2
ECO
37093
37142
Bq
37203
C
37263
Description
New release
Author
KHaworth
Date
8/26/2014
Updates for I/O pinout, KHaworth
sequencer and
command memories
Reorganization of
KHaworth
document, and updates
to command and data
downlink packets,
incorporated feedback
from peer review.
1. Changed primary
KHaworth
control byte data field.
2. Specified MSB first on
clock level voltage
control memories.
3. Separated
correctable and
uncorrectable errors in
the seq, hsk, and prg
memories.
4. Modified
housekeeping interface
and DAC select pins to
do multiplexing on the
FPGA.
5. Added serial upper
registers and increased
size of sequence
memory.
6. Transition from sync
byte to 10-bit
start/stop/data
transfer.
10/6/2014
2/5/2015
6/15/2015
References
Data Sheet
DHU FPGA Specification
37-14011
Reference
37-14010-Bq
Page 5 of 34
Notes
Revision C
Xilinx FPGA 7-series Data
Overview
TESS Focal Plane
Electronics Manual
Analog Devices Data Sheets
1.3
ds180_7Series_Overview.pdf The overview has
a link to all
relevant FPGA
documentation
TBD
AD7894, AD5382
Open Questions
Open questions. Indicated in the document as TBD.
1
The pixel interface readout is not defined.
2
TESS FPE isn’t yet in the ECO system.
2
Scope
The purpose of this document is to describe the firmware requirements for the Transiting
Exoplanet Survey Satellite (TESS) Focal Plane Electronics (FPE) board.
The TESS satellite has four cameras. A camera includes Focal Plane Electronic (FPE) boards. The
FPE boards include the Video board and the Interface board, where the FPE FPGA resides.
One DHU FPGA handles all command/telemetry as well as collecting frames from two FPE FPGAs.
This is shown in the following image.
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Figure 1: FPE/DHU Overview
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3
FPE Firmware Design
3.1
Overview
Figure 2: Block Diagram
Each FPE FPGA provides clocks and control for the four CCDs in one camera. Commands and
telemetry are exchanged with the DHU, and full frame data is transmitted to the DHU. The Artix7, part number XQ7A50T-FG484 will be used for these FPGAs.
There are four primary tasks of this FPGA:
1.
CCD Control
2.
Pixel Transfer
3.
DHU Interface
4.
FPE Housekeeping
3.2
CCD Control
The FPE board has four 18-bit ADCs that interface to each of four CCDs (total sixteen). Four 15MHz SCLK signals and four conversion signals are provided to the ADCs. Each ADC will provide a
serial data input to the FPGA. Over a 24-cycle period, the conversion signal will be high for 8
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cycles, and 16 bits of data will be clocked into shift registers on the FPGA during the remaining
cycles. This results in a 625 kHz serial pixel rate for the CCDs. Because there are 16 output ports
from the camera (4 per CCD), 16 pixels will be available every 1.6 microseconds.
3.3
Pixel Transfer
Sixteen pixels will be transferred to the DHU every 1.6 microseconds.
3.4
DHU Interfaces
3.4.1 Data Downlink (DDL)
Two LVDS twisted pairs will be used to transfer pixels to the DHU until the full frame is complete.
Housekeeping and requested status values will be transmitted between frames.
3.4.2 Serial Synchronous Bus for Command
A serial synchronous RS-422 interface running at 3 MHz will be used to transmit commands to
the FPE from the DHU. It will also be used to upload the bitfile during initialization.
3.5
FPE Housekeeping
Housekeeping will be collected at each frame according to a configurable list held in
programmable memory. A total of 120 housekeeping sources will be sampled and sent to the
DHU, with variable samples per frame.
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4
Interfaces
4.1
External Interfaces Diagram
Figure 3: External Interfaces
4.2
Interface Descriptions
The FPE has the following interfaces:
 CMD: Configuration and Command from the DHU to the FPE.
 DDL: Data Downlink that transfers pixel, housekeeping, and register/memory data from
the FPE to the DHU.
 HSK: Housekeeping control and data input
 CLV: Clock Level Voltage Control
 CCD Clocks: CCD clocking interface
 CCD Data: CCD Pixel Data
 JTAG/Debug
 Oscillator Clock
4.3
CMD Bus
A serial synchronous over RS-422 carries commands from the DHU FPGA to the FPE FPGA. This
bus will operate at 3 MHz. This bus shares a multipurpose data line (DIN) with the configuration
bus.
While in configuration, DIN will transfer the bitfile. After configuration, DIN will be used for
command data.
4.3.1 CMD Packets
This section describes command data over the CMD bus.
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4.3.1.1 Command Packet Format
For commands, between 1 and 1025 32-bit words will be sent per access. The first 32-bit symbol
will be the control value, with bits as shown in the following table.
Bit
31:24
Field Name
SYNC
23:21
OPERATION
Description
x“5A” Used to identify to the control word. If the
command does not have this value, it is dropped,
and an interrupt message is sent to the DHU.
000 – Frame Start. Ignore all other fields. This
starts frame transfer and resets all state machines.
001 – Dump Immediately. Check READ_TYPE field.
Note that after the first Frame Start has been
issued, this command will be ignored. If Frame
Start has been issued, only a reset will allow
memory access.
010 – Reset the FPE. Includes all state machines
and register values, but not memory. If this value
is set, the value in (11:0) must be 0xA96 or else
this command will be ignored.
011 – Write request. Ignore DUMP field.
20:19
READ_TYPE
18:16
WRITE_TYPE
100 – FPE Reprogram Request. If this value is set,
the value in (15:0) must be set to 0x53C.
00 – Housekeeping data
01 – Program memory
10 – Sequencer memory
11 – Housekeeping memory
Note that requesting memory reads is a debug
operation, and should not be done while
transferring frames.
When this is a write command, this field
designates the memory to be loaded.
000 = PMEM Program memory.
001 = SMEM Sequencer memory.
010 = HMEM Housekeeping memory.
011 = VMEM Clock voltage levels memory. (invalid
for dump)
100 = REG Load the registers.
Note that for PMEM, SMEM, VMEM and HMEM, it
is required that the entire memory be written.
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Bit
15:12
11:0
Field Name
Description
Registers may be written individually or
consecutively, depending on REG_ADDR and
REG_NUM fields.
REG_ADDR
Offset start address of write, when accessing
registers. This is ignored when memories are
accessed (all memories must be written from 0).
REG_NUM or
If the operation is a RESET or a REPROGRAM, this
RST_PROG_VALID value must be set as specified in the OPERATION
description.
How many consecutive registers are to be written.
If this is a register write, a value of 0 means the
command will be ignored. If this is a memory
write, a value of 0 means the entire memory will
be written. Note that a value other than 0 will
allow a partial memory write from address 0. This
is for simulation purposes, and should not be used
in normal operation.
4.4
Data Downlink (DDL)
4.4.1 Overview
Raw pixels (overclock and data) are downloaded over the DDL. The two twisted pairs will run at
120 Mbps (60 MHz with DDR) on a TX-only LVDS connection.
Every 1.6 microseconds, sixteen pixels will be split and transferred over the two lines, along with
FPE status. Between frames, housekeeping and requested memory dumps will be transmitted.
A new frame will start when a FRAME_START operation is received from the DHU. This will occur
every 2 seconds.
A reset will occur when a RST_FPE operation is received from the DHU.
In the interim between frame transfers, if requested, housekeeping and/or memory data will be
sent. When no data is available, a sync byte will be sent.
4.4.2 Timing
Raw 16-bit pixels are clocked out over 24 15-MHz (66.7 ns) timeslot periods for a total of 1.6
microseconds. A packet will be generated that combines these pixels with one control byte and
one status byte per line.
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Each line will run at 60 MHz, with data on both clock edges, providing an effective 120 Mbps
transfer rate. Over 1.6 microseconds, 192 bits can be transmitted. Each byte transmitted will have
a start and stop bit, bringing the total to 10 transfer bits per data byte. Each line will transmit
eight pixels of two bytes each, plus one control byte and two status bytes. At 10 bits each, this is
190 bits total. The remaining two bits in the 192 bit transfer will be stop bits.
For more information about the control byte and pixel format, see the data packet descriptions.
4.4.3 Packets
This section describes the download of full-frame images, housekeeping, and requested memory
dumps. All bytes are sent contiguously.
4.4.3.1 Pixel Packets
Images are transmitted in packets of one control byte, two status bytes and eight pixels of two
bytes each per DDL line.
4.4.3.2 Housekeeping Packets
Housekeeping is downloaded at the end of each frame in packets of three control bytes and a
programmable number of housekeeping data values of two bytes each. The HSK_SEL bits in the
control bytes indicate the pointer in the housekeeping memory that determines which values are
to be transferred. The number of values to be transferred is dependent on the value in the
HSK_SAMPLES_PER_FRAME register.
4.4.3.3 Requested Memory Packets
Requested memory values are downloaded on demand at the end of each frame after the
housekeeping packet. These are sent in packets of 32 bytes at a time. There are two control bytes,
with the second byte designating which packet is being sent. The number of packets is dependent
on the type of telemetry requested. The first and last packets are denoted in the control byte.
4.4.3.4 Primary Control Byte (For Synchronization, Pixel, Housekeeping, and Memory)
The following table shows a control byte during normal frame operation. This can represent a
synchronization byte, or control for pixel data or memory/housekeeping.
Bit Field
7:5
Name
DATA
4:0
INFO
37-14011
Description
000 = data packet of upper 8 pixels with 2 bytes
(pixels 8 – 15 of packet) FPE status
001 = hsk packet: housekeeping data and
registers
010 = synchronization byte
011 = mem packet: housekeeping memory
100 = mem packet: sequencer memory
101 = mem packet: program memory
110 = data packet of lower 8 pixels with 2 bytes
(pixels 0 – 7 of packet) FPE status
111 = unused
Sync Byte
10011
Data Packet
4:3 - Unused
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Bit Field
Name
Description
HSK Packet
Mem Packet
Interrupt
2 - FRAME_START (1 = start of
frame)
1 - FRAME_END (1 = end of
frame)
0 - TYPE (Data = 0, Overclock =
1)
4:1 = unused
0 - HSK_SEL bit (8)
Bits 4:0 - unused
Unused (00000)
4.4.3.5 Secondary Control Byte (For Memory)
The following table shows the secondary control byte when a memory dump is in progress.
Bit Field
7:3
Name
NUM_PKT
1:0
FIRST/LAST
Description
The number of the packet being sent,
starting at 0 for each memory block.
00 = Packet in progress
01 = First packet
10 = Last packet
11 = Unused
4.4.3.6 Status Byte 1
The value of this status register will be sent to the DHU after each pixel, housekeeping, and
memory packet. These do not clear until the error has been resolved.
Field Name
CFG_CRC_ERR
Field
7
CFG_ECC_ERR
6
37-14011
Reset Description
Resolution
0
The configuration
memory has reported a
CRC mismatch. This
means that more than
one error has been
detected in a frame. This
is unfixable, and the
configuration must be
reloaded.
0
The configuration
memory has reported a
single or double bit
error. This will be
automatically cleared if
fixed. If unable to fix,
CRC_ERR will be
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REG_ERR
5
0
HSK_ERR
4
0
PRG_ERR
3
0
SEQ_ERR
2
0
CMD_REJECT
1
0
CMD_INVALID
0
0
asserted.
One of the registers has
a parity error.
The housekeeping
memory has an
uncorrectable ECC
error.
The program memory
has an uncorrectable
ECC error.
The sequence memory
has an uncorrectable
ECC error.
An attempt to
write/read memory
while the FPE is enabled
has been made.
A command has been
detected, but it does not
decode to a known
operation.
4.4.3.7 Status Byte 2
The ID of the FPGA.
Field Name
VERSION
Field
7:5
Type
RO
ID
4:0
RO
Reset
Depends on
version
Depends on
camera
Description
The version of the FW.
The status of the strapped
FPGA ID pins
4.4.3.8 Order of Pixel Packet Transfer (lineA/line B)
Order
1
2
3
…
16
17
18
19
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Byte
Primary Control Byte
Pixel8 Data 15:8/Pixel0 Data 15:8
Pixel8 Data 7:0/Pixel0 Data 7:0
Pixel15 Data 15:8/Pixel7 Data 15:8
Pixel15 Data 7:0/Pixel7 Data 7:0
Status Byte 1
Status Byte 2
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4.4.3.9 Order of HSK Packet Transfer
A housekeeping packet consists of the FPE housekeeping data requested, along with the current
status of all registers in the FPE.
The size of the packet is determined by the register HSK_SAMPLES_PER_FRAME. The number of
16-bit samples requested, added to the number of register values (see register section), is the
total data transferred in a HSK packet.
Order
1
2
3
4
5
…
Byte
Primary Control Byte
HSK_SEL(7:0)
Number of bytes to follow
HSK1_upper (15:8)
HSK1_lower (7:0)
HSKN_upper (15:8)
HSKN_lower
Register0(15:8)
Register1(7:0)
…
RegisterM(15:8)
RegisterM(7:0)
4.4.3.10
Order of Memory Packet Transfer
Memory packets are transmitted 32 bytes at a time, with the packet number sent after the control
byte.
Order
1
2
3
…
34
4.5
Byte
Primary Control Byte
Secondary Control Byte
MEM byte 0 + Packet Number*32
MEM byte 31 + Packet Number * 32
CCD Data Input
4.5.1 Overview
The FPGA controls and captures data from 16 Analog to Digital Converters, Part # AD7984 (spec
37-99012.01). Each ADC requires a 15 MHz clock and a conversion bit, and outputs 18 serial data
bits during acquisition phase. Of these bits, only the 16 most significant are clocked out.
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4.5.2 Focal Plane CCD Connections
Readout TBD.
4.5.3 Focal Plane CCD Timing
The ADC components are clocked at 15 MHz. One ADC timeframe is divided in 24 timeslots. Of
these, 18 timeslots are used for conversion, and the remaining 16 timeslots are used to clock out
16 pixels of data simultaneously from the CCDs. The conversion bit in the sequencer memory
determines when the conversion will be asserted, after which the data will be clocked in.
4.6 CCD Clocks
The CCD signals and the ADC conversion are controlled by the sequencer. Before reviewing this
section, review the sequencer and program memories in the Memories section.
Signal Name
IA1, 2, 3
FS1, 2, 3
S1, 2, 3
ID
RG
CNV
Clamp, Int, Hold
Signal Description
Imaging array clocks. These are repeated per
CCD.
Frame store clocks. These are repeated per
CCD.
Serial register clocks
Injection Diode
Reset Gate
ADC conversion
ADC control
4.6.1 Configuration
A combination of the program and sequence memory is used to clock the CCDs. The program
memory is used to select specific sequences. Both memories must be programmed before the first
frame start is received. Memory details can be found in the Memories section.
For example, suppose the following program is desired to run at frame start:
1. Transfer the frame from image array to storage.
2. Transfer out 10 overclock rows of 528 pixels, with each row transfer followed by a
transfer from storage to serial.
3. Transfer out 2064 rows of 10 overclocks, 508 data pixels, and 10 overclocks, with each
row transfer followed by a transfer from storage to serial.
4. Transfer out 10 overclock rows of 528 pixels, with each row transfer followed by a
transfer from storage to serial.
5. Transfer out a row of 528 pixels to flush out the serial register(not data).
6. Integrate.
Four different sequences would need to be in the sequencer memory as follows:
1. Transfer the frame from image array to storage. (143 addresses 0x0A7 – 0x135)
2. Transfer a row from storage to serial. (143 addresses 0x018 – 0x0A6)
3. Transfer a pixel out. (24 addresses 0x000 – 0x017)
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4. Integrate (1 address starting at 0x135)
The program memory is programmed as follows. Note that “--" means not applicable. It will be
ignored by the sequencer and can be filled with 0s.
Prog
Addr
0x000
SEQ
Start
0x0A7
SEQ
End
0x135
Rpt
Type
0
Rpt
Loop
Data
Type
0x2
Fra
me
0
Action
--
Ho
ld
0
1
0x001
0x000
0x017
0
528
--
0
0x1
1
0
1
--
0
0x2
1
--
1
10
0x001
0
0x2
1
Transfer a row of
overclocks out
Transfer a row
from storage to
serial
Repeat from
0x001 10 times
0x002
0x018
0x0A6
0x003
--
0x004
0x000
0x017
0
10
--
0
0x1
1
0x005
0x000
0x017
0
508
--
0
0x0
1
0x006
0x000
0x017
0
10
--
0
0x1
1
0x007
0x008
0x018
--
0x0A6
--
0
1
1
2064
-0x004
0
0
0x2
0x2
1
1
0x009
0x000
0x017
0
528
--
0
0x1
1
0x00A
0x00B
0x018
--
0x0A6
--
0
1
1
10
-0x009
0
0
0x2
0x2
1
1
0x00C
0x000
0x017
0
528
--
0
0x2
0
Flush out a row of
no data
0x00D
0x135
0x135
0
--
--
1
0x2
0
Integrate
4.7
Image array to
storage
Transfer 10
overclocks
Transfer 508
pixels
Transfer 10
overclocks
Storage to serial
Repeat from
0x004 2064 times
Transfer a row of
overclocks
Storage to serial
Repeat from
0x009 10 times
Housekeeping
4.7.1 Overview
Housekeeping monitors temperatures and voltages from 120 different sources and transfers the
information to the DHU. A programmable memory is used in order to control the housekeeping
select. At the end of each frame, the number of values set in the HSK_SAMPLES_PER_FRAME
register will be read from the memory and output to the housekeeping mux on the board. Data
will be collected, with a programmable pause between each sample, and transferred to the DHU.
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4.7.2 Interface Signals
The housekeeping ADCs on the board are controlled by the following signals:
Signal
Dir
Description
from
FPGA
HSK_ADC_SCK
O
15 MHz gated clock. This runs only for 16
clocks when housekeeping data is being
sampled.
HSK_ADC_CNV
O
The active low conversion signal for the ADCs.
HSK_ADC_SDI
I
Serial data input, available after conversion on
the rising edge of the HSK_ADC_SCK.
HSK_ADC_SEL[2] O
Address select for the housekeeping
multiplexors.
HSK_ADC_nn
O
Individual, active high selects for each
multiplexor.
4.7.3 Configuration
To configure the Housekeeping to sample data at each frame:
1. Write a value into the HSK_SAMPLES_PER_FRAME register. If this register remains at 0, no
housekeeping values will be sampled.
2. Write a value into the HSK_TIME_CONV register to indicate the number of 15 MHz clocks
that the conversion signal will be held high for each sample.
3. Write a value into the HSK_TIME_BTN_SAMPLES to indicate the number of 15 MHz clocks
to wait between taking samples.
4. Write a value into the HSK_TOTAL_SAMPLES to indicate how many values are in the
housekeeping memory.
5. Write the sequence of housekeeping desired into the housekeeping memory. See
housekeeping memory format for specifics.
6. Write a ‘1’ into the DUMP_HSK in the Command Packet Control Word at each frame.
The housekeeping state machine will sample the values set in the memory until it reaches the
HSK_SAMPLES_PER_FRAME. On the next frame, it will continue sampling from the point it left off
until it reaches HSK_TOTAL_SAMPLES, when it will return to the beginning of the memory. To
reset the pointer, set the HSK_RST bit in the SOFT_RST register.
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4.8
Voltage Control
CCD clock voltages are controlled via DACs. A 4-bit DCS line is used to control a board decoder
that handles multiple DACs on the Video Board, and four individual CS lines are used to program
specific DACs on the Interface Board. A 15 MHz clock and sync signals are provided for the DACs.
There are 128 16-bit voltage control registers. Once the last value is written, all clock level
voltages will be programmed. In order to reprogram, the memory must be rewritten. Values in
the memory are not stored, so may not be read back.
See the Voltage Memory for programming details.
4.9
JTAG/Debug
A JTAG bus allows configuration for test purposes as well as debug.
There are also 8 general purpose signals available for debug.
4.10 Oscillator Clock
The board oscillator delivers a 60 MHz clock to the FPGA.
4.11 Chip I/O
I/
O
I
PULLUP/
DOWN/
NONE
UP
I
I
UP
UP
I
O
O
O
O
O
O
O
O
O
O
O
I
NONE
Name
FPE_SN[4:0]
Cmd_DIN_pin
Cmd_SCK_pin
osc_clk_60_pin
CCD_FS1_pin[3:0]
CCD_FS2_pin[3:0]
CCD_FS3_pin[3:0]
CCD_IA1_pin[3:0]
CCD_IA2_pin[3:0]
CCD_IA3_pin[3:0]
CCD_InputDiode_pin
CCD_ResetGate_pin
CCD_S1_pin
CCD_S2_pin
CCD_S3_pin
Drive
Str
(mA)
Type
Description
LVCMOS25
Denotes which camera is
hooked to the FPGA.
Command Data from the DHU
Command Clock from the
DHU
60 MHz clock
CCD FS clocks (3) for all
CCDs (4)
LVCMOS33
LVCMOS33
8
8
8
8
8
8
8
8
8
8
8
UP
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
HSK_ADC_Sdi_pin
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
HSK_ADC_0_pin
HSK_ADC_8_pin
HSK_ADC_16_pin
HSK_ADC_32_pin
37-14011
Page 20 of 34
CCD IA clocks (3) for all CCDs
(4)
Input Diode
Reset Gate
CCD Serial register clocks (3)
Housekeeping ADC Serial
data in
HSK Interface Board ADC
select 0
HSK Interface Board ADC
select 8
HSK Interface Board ADC
select 16
HSK Interface Board ADC
Revision C
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
O
8
LVCMOS33
8
8
LVCMOS33
LVCMOS33
HSK_ADC_40_pin
HSK_ADC_48_pin
HSK_ADC_56_pin
HSK_ADC_64_pin
HSK_ADC_72_pin
HSK_ADC_80_pin
HSK_ADC_88_pin
HSK_ADC_96_pin
HSK_ADC_104_pin
HSK_ADC_112_pin
HSK_ADC_120_pin
HSK_ADC_Cnv_pin
HSK_ADC_Sck_pin
O
O
UP
I
UP
HSK_ADC_Sel_pin[2:0]
CCD_ADC_Sdi_pin[15:0]
CCD_ADC_Clamp
CCD_ADC_Int
CCD_ADC_Hold
CCD_ADC_Cnv_pin
CCD_ADC_Sck_pin
CLC_CS8_11_pin[3:0]
CLC_DAC_Din_pin
LVCMOS25
O
O
O
O
O
O
8
8
8
8
8
8
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
O
O
8
8
LVCMOS25
LVCMOS25
O
8
LVCMOS25
O
O
O
O
O
O
O
O
O
8
8
8
8
8
8
8
8
8
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVDS_25
CLC_DAC_Sck_pin
CLC_DCS_0_pin
CLC_DCS_8_pin
CLC_DCS_16_pin
CLC_DCS_24_pin
CLC_DCS_32_pin
CLC_DCS_40_pin
CLC_DCS_48_pin
CLC_DCS_56_pin
CLC_DCS_96_pin
dataA_out_pin_p/n
37-14011
Page 21 of 34
select 32
HSK Interface Board ADC
select 40
HSK Interface Board ADC
select 48
HSK Interface Board ADC
select 56
HSK Interface Board ADC
select 64
HSK Interface Board ADC
select 72
HSK Interface Board ADC
select 80
HSK Interface Board ADC
select 88
HSK Interface Board ADC
select 96
HSK Interface Board ADC
select 104
HSK Interface Board ADC
select 112
HSK Interface Board ADC
select 120
ADC Conversion for
housekeeping
Serial clock for housekeeping
Video Board address select for
housekeeping
Serial Data input from CCDs
(16)
Conversion for CCD ADCs
Clock for CCD ADCs
Clock Level Control Chip
Selects for Interface board—
active low
Clock Level Control DAC Data
Clock Level Control DAC
Clock, 15 MHz
Clock Level Control Interface
Board Selects
Twisted pair LVDS Data to
DHU, Line A. Off-chip
termination FD_100
Revision C
dataB_out_pin_p/n
DebugStatus_pins[7:0]
O
8
LVDS_25
O
4
LVCMOS25
5
Memories
5.1
Memory Overview
Twisted pair LVDS Data to
DHU, Line B. Off-chip
termination FD_100
Debug/Unused
Table 1: List of Memories
Name
Registers
SEQ_MEM
PRG_MEM
HSK_SEL_MEM
VOLT_MEM
5.2
Size
16x16
1024x36
512x64
512x7
128x16
Description
Control and Status Registers
Sequencer Memory
Program Memory
Housekeeping Select Memory
Voltage Levels Control Memory
Memory Descriptions
5.2.1 Program Memory
The program memory consists of programs that control the sequencer. Each program is 64 bits
wide, and formatted as follows:
Bit Field
63:47
46:37
36:27
26
Name
Unused
ST_ADDR
END_ADDR
RPT_TYPE
25:13
RPT
12:4
LOOP
3
HOLD
2:1
DATA_TYPE
0
FRAME
37-14011
Description
Start address in the Sequence memory
End address in the Sequence memory
0 = Repeat the sequence the number of times indicated in
the RPT field.
1 = Repeat a number of consecutive sequences the
number of times indicated in the RPT field.
How many times to repeat a sequence, or a set of
consecutive sequences. Note that 0 or 1 has the same
result—no repeat is executed.
If RPT_TYPE = 1, then loop back to this program memory
address RPT number of times.
Continue to process this sequence indefinitely (until
Frame Start resets).
00 = image data
01 = overclock
10 = no data (will NOT be transferred to DHU)
11 = unused
0 = Frame transfer in progress
Page 22 of 34
Revision C
1 = Frame transfer not in progress
5.2.2 Sequence Memory
The sequence memory consists of programs that control CCD clocks. Each sequence is 33 bits
wide, and formatted as follows:
Bit Field
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
37-14011
Name
CCD_SU_Clock1
CCD_SU_Clock2
CCD_SU_Clock3
CCD4_IA_Clock1
CCD4_IA_Clock2
CCD4_IA_Clock3
CCD3_IA_Clock1
CCD3_IA_Clock2
CCD3_IA_Clock3
CCD2_IA_Clock1
CCD2_IA_Clock2
CCD2_IA_Clock3
CCD1_IA_Clock1
CCD1_IA_Clock2
CCD1_IA_Clock3
CCD4_FS_Clock1
CCD4_FS_Clock2
CCD4_FS_Clock3
CCD3_FS_Clock1
CCD3_FS_Clock2
CCD3_FS_Clock3
CCD2_FS_Clock1
CCD2_FS_Clock2
CCD2_FS_Clock3
CCD1_FS_Clock1
CCD1_FS_Clock2
CCD1_FS_Clock3
CCD_S_Clock1
CCD_S_Clock2
CCD_S_Clock3
CCD_RG
CCD_ID
Int
Hold
Clamp
CNV
Description
Serial upper register clock 1
Serial upper register clock 2
Serial upper register clock 3
Imaging Array Clock 1 CCD4
Imaging Array Clock 2 CCD4
Imaging Array Clock 3 CCD4
Imaging Array Clock 1 CCD3
Imaging Array Clock 2 CCD3
Imaging Array Clock 3 CCD3
Imaging Array Clock 1 CCD2
Imaging Array Clock 2 CCD2
Imaging Array Clock 3 CCD2
Imaging Array Clock 1 CCD1
Imaging Array Clock 2 CCD1
Imaging Array Clock 3 CCD1
Frame Store Clock 1 CCD4
Frame Store Clock 2 CCD4
Frame Store Clock 3 CCD4
Frame Store Clock 1 CCD3
Frame Store Clock 2 CCD3
Frame Store Clock 3 CCD3
Frame Store Clock 1 CCD2
Frame Store Clock 2 CCD2
Frame Store Clock 3 CCD2
Frame Store Clock 1 CCD1
Frame Store Clock 2 CCD1
Frame Store Clock 3 CCD1
Serial register clock 1
Serial register clock 2
Serial register clock 3
Reset Gate
Injection Diode
ADC Int
ADC De-Int
ADC Clamp
ADC Conversion
Page 23 of 34
Revision C
5.2.3 Housekeeping Memory
The housekeeping memory consists of select values to choose a specific housekeeping component
to sample. Each value is 7 bits wide, and formatted as follows:
Bit Field
6:3
2:0
Description
Selects which housekeeping ADC is addressed.
0 = HSK_ADC_0
1 = HSK_ADC_8
2 = HSK_ADC_16
3 = HSK_ADC_24
4 = HSK_ADC_32
5 = HSK_ADC_40
6 = HSK_ADC_48
7 = HSK_ADC_56
8 = HSK_ADC_64
9 = HSK_ADC_72
10= HSK_ADC_80
11 = HSK_ADC_88
12 = HSK_ADC_96
13 = HSK_ADC_104
14 = HSK_ADC_112
15= HSK_ADC_120
Provides select line for housekeeping ADC. Output to
HSK_ADC_SEL(2:0).
5.2.4 Voltage Control Memory
The voltage control memory consists of values to program FPE clock level voltages via DACs. The
values can also be used to reset the DACs. Each value is 16 bits wide, and formatted as shown in
the following table. Data is sent MSB first (bit 15 down to bit 0). Details can be found in spec sheet
AD5329 (37-99012).
Bit Field
15
14:12
11:0
Name
Control
Address
Data
The DAC selected is dependent on upper bits of the address. The output signals CLS_DCS_*_pin
are toggled as shown in the following table, where * is the DAC Addressed.
Address 6:3
0
1
37-14011
DAC Addressed
0
8
Page 24 of 34
Revision C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
32
40
48
56
64
72
80
88
96
Unused
Unused
Unused
5.2.4.1 Software Programming of Clock Level Voltage Memory
The clock level voltage memory must be completely filled before DAC writes will take place.
If it is necessary to skip a DAC value, enter x”FFFF” into the data at the corresponding address.
If it is necessary to perform a reset, follow instructions in the AD5328 document, and set the 11:0
bits (designated as ‘don’t cares’ in the document) to 0’s.
Details of the DAC designations can be found in the TESS Focal Plane Electronics Manual.
Example:
To program a voltage value of +6.0 (1190) into the Serial High DAC, CCD3:
1. Check Table 7 of the TESS Focal Plane Electronics Manual. The Clock Driver Group is
specified as 10CCXXX, where CC is the CCD and XXX is the specific Clock Driver. In this
case, CC is “11” and XXX is “010”.
2. In Clock Level Voltage memory address “1011010”, program “0 101 0100 1010 0110”.
This represents a control byte of ‘0’, an address of “101”, and data of 1190, converted to
binary.
5.2.4.2 Firmware Execution of DAC writes
Once all memory locations have been written, a state machine will commence programming the
DACs from the first to the last address of the memory. Between each DAC write, a clock cycle of
66.7 ns is inserted. This is to meet the timing requirement of the AD5328 specification.
Any data values of x”FFFF” will be skipped.
For the value set in the example above, when address “1011010” is reached, the DCS will be set to
“1010”, the CS8_11 will be set to “1101”, and the data “0101010010100110” will be sent out, MSB
first.
37-14011
Page 25 of 34
Revision C
6
Registers
6.1
Register Writes
The registers are 16 bits wide, and can be written via the CMD interface individually or
consecutively. If written consecutively, writes to read-only bits will be ignored.
6.2
Register Reads
Read/write register values can be dumped either at the end of the frame, or immediately. An
immediate dump is for debug purposes only and can’t be used while processing pixels.
6.3
Register Address Map
Table 2: Register Address Map
Address
Name
Housekeeping Control
0x00
HSK_TIME_CONV
0x01
HSK_TIME_BTN_SAMPLES
0x02
HSK_TOTAL_SAMPLES
0x03
HSK_SAMPLES_PER_FRAME
0x04
0x05
CHARGE_PUMP_ENA
FORCE_STATUS
Sequence Control
0x06
PRG_FS_PTR
Debug (sent with housekeeping, but not writeable)
0x07
FRAMES_XMT
0x08
TEST_MODE
0x09
HSK_SBIT_ERR_CNT
0x0A
SEQ_SBIT_ERR_CNT
0x0B
CMD_SBIT_ERR_CNT
6.4
Register Descriptions
6.4.1 PRG_FS_PTR
This register contains the address where the command buffer will start when the Frame Transfer
Start command is received.
Field Name
CMD_PTR
37-14011
Field
8:0
Type
RW
Reset
0
Page 26 of 34
Description
Address pointer for the
command memory.
Revision C
6.4.2 HSK_TIME_CONV
The number of 15 MHz clocks to hold the housekeeping ADC conversion signal high.
Bit Field
CONV
Bit#
7:0
Access
RW
Reset
0
Description
Number of 15 MHz clocks
to assert conversion.
6.4.3 HSK_TIME_BTN_SAMPLES
The number of 15 MHz clocks to wait between samples for the signals to settle.
Bit Field
SETTLE
Bit#
15:0
Access
RW
Reset
0
Description
Number of 15 MHz clocks
to wait for next sample.
6.4.4 HSK_TOTAL_SAMPLES
This register denotes the number of consecutive housekeeping sample requests in the memory.
This allows the user to only fill as many housekeeping samples as required. Requests must be
consecutive starting from 0.
Bit Field
NUM_MEM_
SAMPLES
Bit#
8:0
Access
RW
Reset
0
Description
Number of consecutive
housekeeping values in the
memory.
6.4.5 HSK_SAMPLES_PER_FRAME
This register denotes the number of housekeeping samples taken per frame. If this is set to 0, no
housekeeping will be transferred, regardless of the state of the DUMP_HSK bit in the Command
from the DHU. The maximum allowed is 32.
Bit Field
PER_FRAME
Bit#
5:0
Access
RW
Reset
0
Description
Number of consecutive
housekeeping values in the
memory. Maximum
allowed is 32.
6.4.6 CHARGE_PUMP_ENA
Enables clock (oscillator frequency/96) output for the charge pumps that make ±30 V.
Bit Field
CP_ENA
Bit#
0
Access
RW
Reset
0
Description
1 = Enable Charge Pump
0 = Disable Charge Pump
6.4.7 FORCE_STATUS
This is for debug purposes only. In order to test out all status bits, this register can be written to
force errors to be transmitted in the status byte (see section Status Byte 1).
37-14011
Page 27 of 34
Revision C
Bit Field
CFG_CRC_ERR
Bit#
7
Access
RW
Reset
0
CFG_ECC_ERR
6
RW
0
REG_ERR
5
RW
0
HSK_ERR
4
RW
0
PRG_ERR
3
RW
0
SEQ_ERR
2
RW
0
CMD_REJECT
1
RW
0
CMD_INVALID
0
RW
0
Description
The configuration memory
has reported a CRC
mismatch. This means that
more than one error has
been detected in a frame.
This is unfixable, and the
configuration must be
reloaded.
The configuration memory
has reported a single or
double bit error. This will
be automatically cleared if
fixed. If unable to fix,
CRC_ERR will be asserted.
One of the registers has a
parity error.
The housekeeping memory
has an uncorrectable ECC
error.
The program memory has
an uncorrectable ECC error.
The sequence memory has
an uncorrectable ECC error.
An attempt to write/read
memory while the FPE is
enabled has been made.
A command has been
detected, but it does not
decode to a known
operation.
6.4.8 FRAMES_XMT
This register reports how many frames have been transmitted since last reset, for debug
purposes. Rolls over at max. This is transmitted with the housekeeping packet, but can’t be
written.
Field Name
FRAMES_XMT
Field
15:0
Type
RO
Reset
0
Description
Number of frames
transmitted since last
reset.
6.4.9 TEST_MODE
This register allows control over test data sent. Test data replaces incoming CCD data over the
sixteen ADC inputs. This is transmitted with the housekeeping packet, but can’t be written.
37-14011
Page 28 of 34
Revision C
Bit Field
MODE
Bit#
1:0
Access
RW
Reset
0
Description
Test modes, described in
the DFT section.
00 = Normal operation
(data from CCDs,
sequencer)
01 = Algorithm 1.
10 = Algorithm 2.
11 = Algorithm 3.
6.4.10 HSK_SBIT_ERR_CNT
This is how many single-bit errors the housekeeping memory has detected and corrected since
the last reset. This is transmitted with the housekeeping packet, but can’t be written.
Bit Field
SBIT_ERR
Bit#
15:0
Access
RW
Reset
0
Description
Number of single-bit errors
corrected.
6.4.11 SEQ_SBIT_ERR_CNT
This is how many single-bit errors the sequence memory has detected and corrected since the
last reset. This is transmitted with the housekeeping packet, but can’t be written.
Bit Field
SBIT_ERR
Bit#
15:0
Access
RW
Reset
0
Description
Number of single-bit errors
corrected.
6.4.12 CMD_SBIT_ERR_CNT
This is how many single-bit errors the command memory has detected and corrected since the
last reset. This is transmitted with the housekeeping packet, but can’t be written.
Bit Field
SBIT_ERR
Bit#
15:0
7
Resets
7.1
Power Up
Access
RW
Reset
0
Description
Number of single-bit errors
corrected.
After configuration, the Xilinx Global Synchronous Reset is released, and all flip flops (memory
and registers) are set to a value determined by the initialization in the configuration file.
37-14011
Page 29 of 34
Revision C
7.2
Reset
A software reset is applied as a special operational command from the DHU (see command packet
format section). This reset is synchronized via two flops to each of three clock domains: Clk_30,
Clk_15, and Clk_15_DL.
The Reset sets all state machines to their idle state, resets the SERDES, and sets registers to the
Reset value as described in the Register section.
This does not reset the memories.
7.3
Frame Start
A frame start command resets all state machines to their idle state. This does not reset registers
or memories.
8
Clocks
Table 3: Clocks
Clock Speed
60 MHz
60 MHz
15 MHz
15 MHz
30 MHz
8.1
Name
Osc_Clk
Clk_60_DL
Clk_15_DL
Clk_15
Clk_30
Notes
Oscillator Clock
Fast serial interface
Slow serial interface
System Clock
Sequencer to Program Memory Interface
Clock tree
The following diagram shows the clock tree for the FPE. Note that the BUFR/BUFIO combination
for the SERDES is designed as described in the Xilinx Serial IO documentation.
IBUFG : Xilinx Input Buffer
BUFMR : Xilinx Multiregion Buffer
BUFR : Clock buffer with divide
BUFIO: Clock buffer designed for SERDES IO applications
37-14011
Page 30 of 34
Revision C
9
FPGA Configuration
The Artix-7 FPGA will be in slave mode with a serial synchronous interface of CCLK (a dedicated
pin) and DIN (a multi-use pin) for configuration. The configuration M pins are tied to “111”.
When the FPGA is powered up, it must be loaded via the serial synchronous interface. Once this is
complete, DIN will be reused for commanding the FPE.
A JTAG interface will be provided for lab configuration of the FPGA. Per Xilinx specification, this
interface is always available, regardless of M pin settings.
9.1 Typical Configuration Procedure
When the Data Handling Unit (DHU) is powered up, the Single Board Computer (SBC) loads the
bitfiles into the DHU FPGAs. The FPE FPGAs bitfiles are then loaded via the CMD interface
between the DHU and FPE FPGA. Once the FPE FPGA has been loaded with a bitfile, it starts
sending sync commands over the DDL interface, thus letting the DHU know it’s operational.
10
Conventions
In this design, bit ‘0’ designates the LSB. All transfers will transmit the least significant
byte/word/double word first. Data and memories are little endian.
11
Radiation Mitigation
Open issues: The radiation environment, while extremely low in the TESS mission, has yet to be
fully specified. Mitigation is described below; however, more analysis needs to be done once the
environment is determined. Specifically, how often the events are expected to occur might affect
science requirements.
Upsets can occur in the configuration memory, in the on-chip block RAM, or in the logic itself.
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Page 31 of 34
Revision C
Currently, it is expected that the configuration memory will have upsets at the rate of five per
day. On-chip block RAM and logic data upsets are still unknown.
11.1 Configuration Memory
The Xilinx FPGAs have built in error detection and correction for SEUs in the configuration
memory. Details can be found in Xilinx User Guide ug470_7Series_Config. A FRAME_ECC2
primitive will be instantiated to collect information on the error detection and correction, and
status will be sent in Status Byte 1. In the event of an error that cannot be corrected, the error bit
will persist, and the configuration must be reloaded, either by a command requesting a
configuration scrub, or if that fails, by cycling the power and reconfiguring. This will take
approximately 10 seconds, during which no science data will be collected on this particular
camera. It will not affect other the other cameras.
11.2 On-chip Block RAM
All memories that hold persistent data (sequence, program, and housekeeping) will have ECC.
The status of this will be reflected in Status Byte 1. If an uncorrectable error is found, the FPE
must be disabled, and the memories must be reloaded. This will take less than a frame. While this
occurs, science data will not be collected.
11.3 Design Logic
An upset can occur anywhere in the logic, resulting in a flipped register bit, incorrect science data,
or an error in the interface to the DHU.
11.3.1 Registers
All registers that hold persistent data will have a parity bit that is calculated when the register is
written. These bits will be checked on read. Status Byte 1 will reflect an error. Since the error bit
will not specify which register, all registers must be rewritten. Since the registers are all
housekeeping specific, this will not necessarily stop science data from being collected, though
housekeeping data will not be accurate until the registers are reloaded.
11.3.2 Logic Upset Detection
While the configuration, registers, and block memory have automatic detection, a logic upset will
not be as apparent. The following sections discuss ways to detect a logic upset.
11.3.2.1 Loss of sync/bad downlink control byte
The synchronization byte is transmitted whenever there is no data, and the downlink control
byte is transmitted per packet. This might occur if an SEU occurs in DDL logic or in the data. The
DHU will detect this almost immediately. If it is simply a data bit flip, it will correct itself.
Otherwise, the problem will persist.
11.3.2.2 Frame start/Frame end does not occur when expected
The DHU keeps track of the PPS signal, which starts a frame on alternate assertions. If the control
bytes for the pixel do not send a frame start or end, this might indicate an SEU occurred in the
Sequencer logic or in the Command Decode logic (frame start was not decoded properly). The
DHU will detect this once per frame.
37-14011
Page 32 of 34
Revision C
11.3.2.3 Commands
If an incorrect command is received, a bit will be reflected in the Status Register. This is an
indication that something might be wrong with the command interface. If an upset has occurred
so that command logic is no longer receiving commands, this will be discovered by the DHU when
the next frame is expected, but not transmitted.
11.3.3 Logic Upset Mitigation
There are three possible mitigations for a logic upset, if the error does not correct itself (as
explained in the previous section). These should be tried in the order given, as they are listed
least disruptive to most disruptive.
1. Wait for the next frame. All state machines are automatically reset when a frame start
command is received.
2. Issue a software reset to the FPE. This will require reconfiguring the registers.
3. Power cycle. This will require reloading the bitfile and reconfiguring the memories and
registers.
12
Design For Test (DFT)
12.1 Debug I/O
The following signals will be made available via the Debug bus for observability of functions
while lab testing:
1.
Frame Start Received (will toggle at each receipt)
2.
End of frame (will clear at Frame Start)
3.
Command received (will clear at Frame Start)
4.
Housekeeping sent (will clear at Frame Start)
5.
Clocks on
6.
Test Mode
12.2 Image Generation
Image data is captured from the ADC inputs into shift registers. Data will be generated via an
algorithm according to the TEST_MODE.
13 Current power estimates
The current total power is estimated at 174 MW. However, the I/O Nodes activity has yet to be
specified, which will increase this by a small amount. The following table shows a breakdown of
the power supply.
Source
Vccint
Vccaux
Vcco33
Vcco25
37-14011
Voltage (V)
1
1.8
3.3
2.5
Dynamic (mA)
12
1
4
31
Page 33 of 34
Static (mA)
10
13
1
1
Revision C
VccADC
14
1.8
0
20
Acronyms/Abbreviations
Table 4: Acronyms/Abbrevations
ADC
CCD
CMD
CS
DFT
DDL
DDR
DHU
FFI
FPE
FPGA
FS
GPIO
IA
ID
IG
JTAG
LSB
MSB
OG
RD
RG
S
SBC
SCP
SEU
SUB
TBD
USD
37-14011
Analog to Digital Converter
Charge Coupled Device
Command Bus
Channel Stop
Design for Test
Data Downlink Bus
Double Data Rate
Data Handling Unit
Full Frame Image
Focal Plane Electronics
Field Programmable Gate Array
Frame Store
General Purpose Input/Output
Imaging Array
Injection Diode
Input Gate
Joint Test Action Group (Test Access Port and Boundary Scan)
Least Significant Bit
Most Significant Bit
Output Gate
Reset Drain
Reset Gate
Serial
Single Board Computer
Scupper
Single Event Upset
Substrate
To Be Determined
Upper Serial Drain
Page 34 of 34
Revision C