Design FSM,
Instruction Set
Architecture
Prof. Sin-Min Lee
State Machines
• Construct a sequence detector: 001
Solution:
1) Formulate State Diagram:
0
1
A
0
0
C
B
1
0
1
1
D
2) Construct State Table:
Present State
Next State
Input (x)
0
1
Output (PS)
Z
A
B
A
0
B
C
A
0
C
B
D
0
D
B
A
1
3) Construct Logic Table
Present State
Next State
X=0 Input (x)
Q0
Q1
Q0
Q1
Q0
Output (PS)
Z
A 0
0
0
1
0
0
0
B
0
1
1
1
0
0
0
C 1
1
0
1
1
0
0
D 1
0
0
1
0
0
1
Q1
X=1
4) Extract Logic Equations
Present State
Next State
X=0 Input (x)
Q0
Q1
Q0
Q1
Q0
Output (PS)
Z
A 0
0
0
1
0
0
0
B
0
1
1
1
0
0
0
C 1
1
0
1
1
0
0
D 1
+
0
0
1
0
0
1
Q1
Q 0 = X,
+
1
X=1
Q = XQ1Q 0 + XQ1Q0,
Z = Q1Q0
5) Draw Logic Diagram
X*
+
Q0 = X
D
Q0*
clk
Q+1 = XQ1Q 0 + XQ1Q0
Q0
X
Q1
D
And
Q1
Q0
X
Q1
Q0
Q1
And
O
r
Continue…
Continue…
Z = Q1Q0
Q1
And
Z
Q0
6)Draw functional block diagram
Input
Clock
001
Detect
Output
State Machines
• Construct a soda machine which 1) take only quarters, and
2) deliver a soda when all three quarters are inserted
Solution:
1) Formulate State Diagram:
25C
Not 25C
A
25C
25C
B
25C
C
Not 25C
Not 25C
25C
D
2) Construct State Table:
Present State
Next State
Input (x)
0
1
Output (PS)
Z
A
A
B
0
B
A
C
0
C
A
D
0
D
A
B
1
3) Construct Logic Table
Present State
Next State
X=0 Input (x)
Q0
Q1
Q0
Q1
Q0
Output (PS)
Z
A 0
0
0
0
0
1
0
B
0
1
0
0
1
1
0
C 1
1
0
0
1
0
0
D 1
0
0
0
0
1
1
Q1
X=1
4) Extract Logic Equations
Present State
Next State
X=0 Input (x)
Q0
Q1
Q0
Q1
Q0
Output (PS)
Z
A 0
0
0
0
0
1
1
0
B
0
1
0
0
1
11
0
C 1
1
0
0
1
00
0
0
0
0
D 1
Q +0 = XQ1 + XQ0
0
11
1
Q1
+
1
X=1
Q = XQ 0,
Z = Q1Q0
5) Draw Logic Diagram
X
+
Q 1 = XQ0
And
Q0
D
Q0*
clk
Q0+= XQ1 + XQ0
X
Q1
Q0
D
And
Q0
Q0
X
Q0
And
O
r
Continue…
Continue…
Z = Q1Q0
Q1
And
Z
Q0
6)Draw functional block diagram
Money
Clock
Quarters
Detect
Soda
Moore Machine Vs. Mealy Machine
Moore machine associates its output with the states.
The outputs are represented either within the vertex
corresponding to a state or adjacent to the vertex.
Mealy machine associates its output with the transitions.
Each arc of the input values shows the output values
generated during the transition.
What is “Computer Architecture”
Computer Architecture
is the design of the
computer at the hardware/software
interface.
Computer Architecture = Instruction Set
Architecture + Machine Organization
Computer Architecture
Instruction Set Design
Machine Organization
Computer Interface
Hardware Components
Compiler/System View
Logic Designer’s View
The Instruction Set: a
Critical Interface
software
instruction set
hardware
ISA



The instruction set architecture, or ISA, is much
like the car interface, but for microprocessors.
ISA includes the information needed to interact
with the microprocessor, but not the details of
how microprocessor itself is designed and
implemented.
ISA is the set of all instructions that the
microprocessor can execute.
Language Categories
1.
High-level languages


2.
Assembly languages


3.
Platform-independent: the same code can be run on
computers with different microprocessors and OSs.
C++, Java, Fortran
Specific to a microprocessor
Directly manipulate the data stored in internal components
Machine languages



Instructions are binary
Programs are converted to machine language
Each processor has its own machine language
Compiling and Assembling
High-level language programs are
compiled.
 Assembly language programs are
assembled

Compiling



A program written in high-level language, a
source code, is input to a compiler.
The compiler checks for syntax errors and
generates an object code file, machine language
equivalent of the source code.
A linker combines all object codes and stores it
as an executable file.
 Some
programs use the object code of other
programs.

A loader copies the executable file into memory
Compilation Process
Assembling

Each assembly
language instruction
corresponds to one
unique machine code
instruction.
 Assembler
are much
less complex than
compilers
High-level and Assembly



Most software is written in high-level language.
There are many support tools for high-level
languages.
Assembly language is used in conjunction with
high-level languages to optimize code.
 The
program is no longer platform-independent
Compilation for Java Applets
Assembly Language Instructions
Instruction types:
Data transfer instructions
2. Data operation instructions
3. Program control instructions
1.
Instruction Set Architecture

Instruction set architecture is the attributes of a
computing system as seen by the assembly language
programmer or compiler. This includes
 Instruction
Set (what operations can be
performed?)
 Instruction
 Data
Format (how are instructions specified?)
storage (where is data located?)
 Addressing
Modes (how is data accessed?)
 Exceptional
Conditions (what happens if something
goes wrong?)

A good understanding of computer architecture is
important for compiler writers, operating system
designers, and general computer programmers.
What is ISA?
Aspects of the computer visible to the
programmer:
 Data Types
 Registers
 Instructions
 Addressing
Instruction Set Architecture as an
ADT
“…the attributes of a [computing] system as seen by the
programmer, i.e. the conceptual structure (state) and
functional behavior (operations), as distinct from the
organization of the data flow and controls, the logical
design, and the physical implementation.”
- Amdahl, Blaauw, and Brooks,
1964
instruction
instruction …..
instruction
instruction

Registers + Memory
instruction
instruction
…..
instruction
Instruction Set Architecture as an
ADT
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B
Memory
Memory
63
63
r3
r2
r1
r0
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
3
2
1
0
7
2
0
4
Before Register and Memory
Registers
add r1, r2, r3
r3
r2
r1
r0
PC
8
12
20
2
21
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
··
··
PC
8
12
1
2
20
··
··
Registers
3
2
1
0
7
2
0
4
After Register and Memory
Instruction Set Architecture as an
ADT
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B
Memory
Memory
63
63
r3
r2
r1
r0
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
3
2
1
0
7
2
0
4
Before Register and Memory
Registers
lw r2, 1(r0)
r3
r2
r1
r0
PC
8
7
20
2
22
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
··
··
PC
8
12
20
2
21
··
··
Registers
3
2
1
0
7
2
0
4
After Register and Memory
Instruction Set Architecture as an
ADT
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B
Memory
Memory
63
63
r3
r2
r1
r0
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
3
2
1
0
7
2
0
4
Before Register and Memory
Registers
sw r3, 0(r0)
r3
r2
r1
r0
PC
8
7
20
2
23
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
··
··
PC
8
7
20
2
22
··
··
Registers
3
2
1
0
7
8
0
4
After Register and Memory
Instruction Set Architecture as an
ADT
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B
Memory
Memory
63
63
r3
r2
r1
r0
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
3
2
1
0
7
8
0
4
Before Register and Memory
Registers
beq r0, r1, 2
r3
r2
r1
r0
PC
8
7
20
2
24
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
··
··
PC
8
7
20
2
23
··
··
Registers
3
2
1
0
7
8
0
4
After Register and Memory
Instruction Set Architecture as an
ADT
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B
Memory
Memory
63
63
r3
r2
r1
r0
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
3
2
1
0
7
8
0
4
Before Register and Memory
Registers
j 15
r3
r2
r1
r0
PC
8
7
20
0
15
(j 15)
(beq r0, r1, 2)
24
23
22
21
20
(sw r3, 0(r0))
(lw r2, 1(r0))
(add r1, r2, r3)
··
··
PC
8
7
20
0
24
··
··
Registers
3
2
1
0
7
8
0
4
After Register and Memory
Data Types
Unsigned Integers
 Signed Integers
 Characters
 Floating-point Numbers

Unsigned Integers

Stores the integer in standard binary
format
00101011 = 1 + 2 + 8 + 32 = 43
Signed Integers

Stores the integer in two’s complement
format to denote sign
Steps to convert signed integer to base 10:
 Store leading bit, 1 = negative, 0 = positive
 Invert all bits
 Add 1
Characters

Represented by integer values
Many different character encodings exist:
 ASCII
 UNICODE
 UTF-8
 UTF-16
Floating-point Numbers
Four components in a floating-point number:
 Sign
 Mantissa
 Radix
 Exponent
Registers
Registers provide a variety of services:
 Instruction Counter
 Register-to-Register Operations
 Memory-to-Register Operations
 Memory-to-Memory Operations
 Processor Status
Instruction Counter Register

All von Neumann machines have an
instruction counter which is a register
Register-to-Register Registers
Operate on one register using another
register (ADD)
 Supported by all ISA’s

Memory-to-Register Registers
Operate on memory using a register
(LOAD, STORE)
 Not supported by all ISA’s

Memory-to-Memory Registers
Operate on one memory location using
another memory location (STRCMP)
 Not supported by all ISA’s

Processor Status Registers
A collection of registers that indicate the
current state of the processor (Carry,
Interrupt, Zero)
 Different ISA’s use different status
registers

Instructions
Categories of instructions:
 Operate
 Memory Access
 Control
 Miscellaneous
Operate Instructions
Typical operations include:
 Arithmetic (ADD, SUB, MUL, DIV)
 Logical (AND, OR, NOT, XOR)
 Shift (ROL, ROR)
 Character (STRCMP)
 Stack (PUSH, POP)
Memory Access Instructions
Typical operations include:
 Load (LODSB)
 Store (STOSB)
Control Instructions
Conditional Branch (JZ, JC, JO, JS)
 Unconditional Branch (JMP)

Miscellaneous Instructions
Input/Output (IN, OUT)
 Interrupts (CLI, INT, IRET)
 Halt
 Privileged

Addressing
Register Addressing
 Memory Addressing

Register Addressing

When an operand is taken from a register
it is called register addressing
Memory Addressing
Logical Address Space (sequential
memory locations)
 Physical Address Space (many types
exists: absolute addressing, indirect
addressing, etc.)

ISA Examples
MIPS
 Motorola 6800
 ARM
 SPARC
 PowerPC
 x86
 IA-64

What is an ISA (Instruction Set
Architecture)?






Machine language instructions
Registers
Data representation (endianess, word size)
Addressing methods
Privilege modes
ISA is not: CPU speed, cache size, pipelines,
etc.
Instruction Set Architecture
Organisation of storage: registers, memory
 Representations of data
 Instruction set
 Instruction formats
 Modes of addressing and accessing data
 Exceptional conditions

Instruction Set Architecture
Advantage: enables different
implementations of the same architecture
 Disadvantage: may prevent using new
innovations

Machine Organisation
Implementation, capabilities and
performance characteristics of
functional units
 Interconnections of these units
 Information flows between these units
 Control of information flow

Block Diagram of a Computer
CPU
ALU
Input
Unit
Output
Unit
Control
Unit
Register
Unit
Memory
So, let’s look at several ISA’s
Example ISAs (Instruction Set Architectures)
 IBM 360
(v1,v…) Defines the
Mainframe Generation
 Digital
PDP-11
(v1,v3)
PRISM
(v1)
1989-92
(v1, v3)
1992-97
Defines the
PC Generation1987-95
Vax-11
 Digital
Defines the
Minicomputer
Generation
 Digital Alpha
 Sun
Sparc
(v8, v9)
 SGI
MIPS
(MIPS I, II, III, IV, V)
(8086,80286,80386,
80486,Pentium, MMX, ...)
Itanium/I64
 Intel
1964 - ?
1973-78
1978-92
1986-96
1978-00
2002-
Evolution of Instruction Sets
Single Accumulator (EDSAC 1950)
Accumulator + Index Registers
(Manchester Mark I, IBM 700 series 1953)
Separation of Programming Model
from Implementation
High-level Language Based
(B5000 1963)
Concept of a Family
(IBM 360 1964)
General Purpose Register Machines
Complex Instruction Sets
(PDP-11, Vax, Intel 432 1977-80)
Load/Store Architecture
(CDC 6600, Cray 1 1963-76), FP-11
RISC
(Mips,Sparc,HP-PA,IBM RS6000, . . .1987)
Instruction Set Architecture:
What Must be Specified?
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
 Instruction
Format or Encoding
How is it decoded?
 Location of operands and result
Where other than memory?
How many explicit operands?
How are memory operands located?
Which can or cannot be in memory?
 Data type and Size – 16, 32, 64- bit, …
 Operations
What are supported
 Successor instruction
Jumps, conditions, branches
Fetch-decode-execute is implicit! –
Von Neumann
Two well known ISA’s in further
detail
MIPS R3000 Instruction Set Architecture
(Summary) – Supposedly a True RISC

Instruction Categories
R0 - R31

Load/Store
 Computational
 Jump and Branch
 Floating Point
PC
HI
LO
coprocessor

Registers

Memory Management
 Special
OP
rs
rd
rt
3 Instruction Formats: all 32 bits wide
OP
OP
rs
rt
sa
funct
immediate
jump target
Q: How many already familiar with MIPS or ALPHA ISA?
A "Typical" RISC – 32 bit
 32-bit
fixed format instruction (3 formats)
 32 32-bit GPR (R0 contains zero, DP
take pair of Registers)
 3-address, reg-reg arithmetic instruction
 Single address mode for load/store:
base + displacement
no
indirection
 Simple
branch conditions
 Delayed branch -
ALPHA AXP Instruction Set Architecture (Summary) – 1st
True 64 bit Arch


True 64-bit (RA’s are 64 bit, VA is 64-bit)
Instruction Categories
 Load/Store
 Computational
 Jump and Branch
 Floating Point – both VAX-11, IEEE
 Memory Management & MP lock

Special, e.g.
Vax-11 all
modes
4 Instruction
Formats:
32 bits wide
32
25
21 20
Registers
RA
RB
OP
RA
RB
OP
RA
number
0
R0 - R31
16 15
OP
OP
64
PC
LPAR
Lock Phy Adr Reg
LFR
5
function
Lock Flag Reg
4
0
RC
Operate Intr
Displacement
Load/Store
Displacement
Branch Instr
Palcode Instr
ALPHA AXP







Load/Store architecture (means separate memory references from
execution stream)
 E.g., PDP-11 and Vax-11’s you have ADD RA, Mem instructions
True 64-bit architecture
 32 64-bit integer and 32 64-bit Floating Point registers – all
operations are done on 64-bit
Memory is addressed via 64-bit little-endian byte addresses
Four floating point data types supported
 VAX F_floating (32 bit)
 VAX G_floating, VAX D_floating (64 bit)
 IEEE single (32 bit)
 IEEE double (64 bit)3-address, reg-reg arithmetic instruction
Single address mode for load/store:
base + displacement
 no indirection
Simple branch conditions
Instruction Set can be subset (e.g., no Floating Point)