Ch.9 CPLD/FPGA Design
TAIST ICTES Program
VLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
Outline
1. CPLD & FPGA
2. Design Procedure
2
9.1 Programmable Device
FPGA
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Reconfigurable LSI or Programmable Hardware
Programmable Logic Array and Programmable
Interconnection
Programmed by Reconfigurable Data
Xilinx and Altera
Prototyping of ASIC (different physical
condition)
4
The Programmable Marketplace
Q1 Calendar Year 2005
PLD Segment
Actel
Lattice
5% 7%
FPGA Sub-Segment
Xilinx
QuickLogic: 2%
Other: 2%
58%
33%
51%
31%
Altera
Xilinx
Altera
Two dominant suppliers, indicating a maturing market
Source: Company reports
Latest information available; computed on a 4-quarter rolling basis
ECE 545 – Introduction to VHDL
11%
All Others
FPGA families
Low-cost
Xilinx
Altera
Spartan 3
Spartan 3E
Spartan 3L
Cyclone II
ECE 545 –
Introduction to VHDL
High-performance
Virtex 4 LX / SX / FX
Virtex 5 LX
Stratix II
Stratix II GX
Xilinx and Altera FPGA
Xilinx
#gates
Program
Clock
Note
Virtex
50k-10M
SRAM
550MHz
System
Spartan
5k-300k
SRAM
250MHz
ASIC
XC9500
13k-85k
SRAM
100MHz
Altera
#gates
Program
Clock
Note
Stratix
180k
SRAM
500MHz
High end RAM & Multiplier
Cyclone
16k
SRAM
200MHz
Low cost
FLEX
10k-250k
SRAM
200MHz
High Speed
MAX(CPLD)
600-10K
EEPROM
150MHz
Low Price
9.2 PLD
ＣＰＬＤ
9
Function Block in CPLD
Example of PLD Design
X=0
000
State Transition Table
X=1
001
011
111
110
100
Y=1
S１ S２ S３ X
S１ S２ S３ Y
0 0
0 0
0 0
0 0
0 0
0 1
0 0
1 0
0 0
1 *
0 1
1 0
0 1
1 *
1 1
1 0
1 1
1 *
1 1
0 0
1 1
0 *
1 0
0 0
1 0
0 *
0 0
0 1
PLA & FF Realization
S１ S２ S３ X
DS１ DS２ DS３ Y
0 0
0 0
0 0
0 0
0 0
0 1
0 0
1 0
0 0
1 *
0 1
1 0
0 1
1 *
1 1
1 0
1 1
1 *
1 1
0 0
1 1
0 *
1 0
0 0
1 0
0 *
0 0
0 1
S1
DS1
S2
DS2
S3
DS3
PLA
AND-OR
X
Y
DFF
DFF
DFF
9.3 FPGA
Xilinx FPGA
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
ECE 545 –
Introduction to VHDL
Xilinx CLB
Configurable logic block (CLB)
CLB
CLB
CLB
CLB
ECE 545 –
Introduction to VHDL
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
LUT <Look Up Table>
LUT Structure
Interconnection
Logic Block
Advantages and Disadvantages

Advantages
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Disadvantages
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19
Short TAT(Turn-Around Time)
Small NRE (Non Recurrent Expense) Fee
Logic and Timing Design are required.
Full amount of IP (Intellectual Property)
Slow speed and Large Chip Area
High cost for volume manufacturing
9.4 FPGA Design
FPGA Design
RTL
RTL Simulation
Logic Synthesis
LSI Tool
FPGA Tool
Synthesis
Netlist
Gate Assignment
LE Place and Rout
Configuration
Data
Functional Verification
FPGA Design Flow
１bit Adder/Subtracter
4bit Adder/Subtracter
FPGA Design
Three-Step Design Compilation in Quartus II Software
1. Run the New Project Wizard
a. Specify project directory, name, and top-level entity.
b. Specify project design files.
c. Specify Altera device family for the design.
d. Specify device (or specify device information for
automatic device selection).
e. Specify other EDA tools to be used for this project.
f. Review project settings.
2. Run the TimeQuest Timing
Analyzer
a. On the Process menu, click Start Analysis & Synthesis to build a
netlist in preparation for TimeQuest timing analyzer use.
b. On the Tools menu, click TimeQuest Timing Analyzer to launch
TimeQuest analyzer.
i. On the Netlist menu, click Create Timing Netlist and select Postmap to create the timing netlist with timing delay information.
ii. Specify your design timing constraints using the analyzer’s graphical
user interface (GUI) or by using the Synopsys Design Constraint
(SDC) text editor.
c. On the Assignment menu, click Timing Analysis Settings to specify
TimeQuest analyzer as the timing analysis tool and to add your SDC file
to the project.
Quartus II Assignment menu provides all settings and assignments
for the project.
3. Compile the Design
a. Select one of the following methods to compile the design:
i. On the Processing menu, click Start Compilation.
ii. On the menu toolbar, click .
iii. On the Processing menu, click Compiler Tool and click Start.
b. When compilation is complete, refer to the Compilation Report window to
view information on compiler settings, resource usage, and compilation
equations.
Timing analysis is also performed during compilation on the current design,
and the Compilation Report window includes the timing information.
9.5 Optimization
Trade-offs
speed
area
power
testability
Speed optimization (1)
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better architecture (e.g., CLA vs. ripple
carry adder)
pipelining
parallel processing
optimization options of synthesis and
implementation tools
Speed optimization (2)
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reducing fanout of control signals
better state encoding
registered outputs from the state machine
ECE 545 –
Introduction to VHDL