LOCx2, a Low-latency, Low-overhead, 2 × 5.12-Gbps Transmitter
ASIC for the ATLAS Liquid Argon Calorimeter Trigger Upgrade
Le Xiao,a,b Xiaoting Li,a Datao Gong,b,*
Jinghong Chen,c Di Guo,b,d Huiqin He,a,b,e Guangming Huang,a Suen Hou,f
Chonghan Liu,b Tiankuan Liu,b Xiangming Sun,a Ping-Kun Teng,f Bozorgmehr Vosooghi,c Annie C. Xiang,b Jingbo Ye,b Yang You,g
a Department of Physics, Central China Normal University,Wuhan, Hubei 430079, P.R. China
b Department of Physics, Southern Methodist University, Dallas, TX 75275, USA
c Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004, USA
d State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026, China
e Shenzhen Polytechnic, Shenzhen 518055, P.R. China
f Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan
g Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75275, USA
* dgong@mail.smu.edu
Introduction
On-detector, rad-tol
• The ATLAS Liquid Argon calorimeter (LAr) Phase-I trigger upgrade calls for
a data transmission rate of 204.8 Gbps for each front-end board (LTDB) [1].
• The optical link on the transmitter side consists of a transmitter ASIC LOCx2
and a custom optical transmitter module MTx.
• LOCx2 is a two-channal transmitter ASIC. Each channel receives data from
the upstream ADCs [2], encodes the data, and outputs them in serial at a
speed of 5.12Gbps.
• The transmitter ASIC is fabricated in a commercial 0.25-µm Silicon-onSapphire CMOS technology for radiation-tolerance.
• The latency budget of the optical link is 150 ns.
• The power consumption budget of the transmitter ASIC is 1 W.
Off-detector, COTS
FPGA
Encoder
Optical
fiber
Laser
driver
Serializer
Optical transmitter
Transmittter
TIA
deserializer
Decoder
Receiver
Optical receiver
The block diagram of the optical link in
ATLAS LAr trigger phase-I update
The design of AISC
LOCX2
Encoder
Div64
2.56 GHz
clock
A Frame
A Data X 4
ADC A
16-bit data
5.12
Gbps
A Clock
LOCic16B
B Frame
320MHz
16:1
Serializer
CML
Driver
40 MHz
Clock
MTx
B Data x 4
ADC B
UP
LVDS
Rec
Charge
pump
PFD
LC-PLL
BCID_Reset
The block diagram of PLL
SDA
SCL
I2C Slave
Address
GBT based
Control link
C Frame
C Data x 4
16-bit data
5.12
Gbps
C Clock
LOCic16B
D Frame
320MHz
16:1
Serializer
CML
Driver
D Data x 4
D Clock
The block diagram of LOCx2 ASIC
Div2
Div2
2.56GHz Clock
from PLL
Div2
4
Data 8
2:1
Mux
4
2:1
Mux
2
2
2:1
Mux
2:1
Mux
Serial Data
@ 5.12Gbps
Serializer
The block diagram of serializer
Layout of the LOCx2 ASIC
• Each Serializer unit consists of 4 stages of 2:1 multiplexers
in a binary tree structure. All 2:1 multiplexer are based on
static CMOS D flip flops for single-event effect (SEE)
immunity.
QFN packaged LOCx2 ASIC
A Frame
LVDS
Rec A Frame
A Clock
LVDS
Rec A Clock
B Data
B Frame
B Clock
PRBS Clk
16
Data to
Serializer
Frame Clock
A Data
8x4
Synch
FIFO
16
Data
8
CRC
Generator
CRC Clk
4
B Data
16
LVDS
Rec B Frame
LVDS
Rec B Clock
Scrambler
SCR Clk
320MHz Clock
From PLL
320MHz LOC Clock
The block diagram of LOCic encoder
CML Driver
Data 8
A Data
LVDS
Rec
8
PRBS
Generator
4
LVDS
Rec
4
ADC B
• The PLL has four tuning frequency bands selected through
the I2C interface. The tuning range of LC-VCO is from 1.86
GHz to 2.98 GHz at the nominal process corner and 55 C.
• Both the bandwidth of the LPF and the charge pump
current are programmable, thus the loop bandwidth of the
PLL is programmable from 0.5 to 2.5 MHz.
BCID_Reset
Frame Builder
ADC A
40 MHz Ref Clk
ADC D
4
PLL
2.56 GHz
ADC C
LC
VCO
LPF
Down
B Clock
GBT Based
Control link
From GBTx
BCID_Reset
• The ASIC uses a custom line code called LOCic [3].
• Each frame consists of 128 bits, including 8-bit frame header,
112-bit payload and 8-bit frame trailer.
• The payload is scrambled before transmitted, whereas the
frame header and trailer are not scrambled.
• 12-bit BCID information is embedded in the frame header
automatically.
• The overhead is 14.3% (= 16/112).
The test system and measurement results
Clock Board
KC705 FPGA Evaluation Board
SDA
DATA[3:0] x 4
SCK x 4
FCK x 4
PLL
BCID Reset Gen
BCID
Reset
Connector
640
MHz
NEVIS ADC Emulator x 4
SCL
LOCx2
Test
Test Clock
Board
Oscilloscope
Receiver x 2
USB
PC
Error
Logger
LOCic
Decoder
16
16
I2C
Master
40 MHz
Trig Clock
40MH
z Ref
Clock
320 MHz
MGT
Deserializer
5.12Gbps
Channel0
5.12Gbps
Channel1
The block diagram of test setup
The eye diagram of LOCx2 output at 5.12Gbps
PLL turning range
PLL random jitter
Serial date output rise time
Serial date output fall time
2.0-3.1 GHz
1 ps (RMS)
70 ps
64 ps
Serial date output deterministic jitter
Serial date output random jitter
Serial date output total jitter
Serial date output amplitude
Serial date output BER
A picture of test setup
Conclusion and outlook
• An transmitter ASIC, LOCx2, is designed and tested for the
ATLAS LAr Calorimeter trigger upgrade.
• LOCx2 consists of two channels and each channel encodes
ADC data with an overhead of 14.3% and transmits serial data
at 5.12 Gbps with a latency of less than 27.2 ns. The power
consumption of the transmitter is 842.5 mW.
• The next version will interface with both ASIC and COST ADCs
28 ps
1.5 ps (RMS)
42 ps (peak-peak)
445mV (peak-peak)
< 10-12
Function block
Latency (ns)
8.4-11.6
FIFO
6.25
Scrambler & CRC gen
Simulation
3.125
Frame Builder
TX
6.25
Serializer
24.0-27.2
Total LOCx2
Deserializer
28.5-31.4
Measurement
Data Extractor
9.4
RX
Descrambler
3.1
CRC Check
3.1
Total FPGA
44.1-47.0
Total optical link
68.1-74.2
Latency of the optical link
Functional blocks Power consumption (mW)
LC-PLL
LOCic
Serializer
CML Driver
Clock Buffers
SLVS Receivers
Total
PLL and LOCx2 output measurment
Power consumption of LOCx2 chip
Acknowledgments
This work is supported by US-ATLAS R&D program
for the upgrade of the LHC, the US Department of
Energy Grant DE-FG02-04ER1299. We are grateful to
Drs. Hucheng Chen and Hao Xu of Brookhaven
National Laboratory for help on test and firmware
development, Dr. Nicolas Dumont Dayot of LAPP for
discussion on decoder implement.
52.5
192.5
350.0
150.0
22.5
75.0
842.5
References
[1] ATLAS Collaboration, ATLAS liquid argon calorimeter Phase-I upgrade technical
design report, CERN-LHCC-2013-017 and ATLAS-TDR-022, September 20, 2013.
[2] J. Kuppambatti, et al, A radiation-hard dual channel 4-bit pipeline for a 12-bit 40
MS/s ADC prototype with extended dynamic range for the ATLAS Liquid Argon
Calorimeter readout electronics upgrade at the CERN LHC, 2013 JINST 8 P09008
[3] B. Deng, et al, A line code with quick-resynchronization capability and low latency
for the optical data links of LHC experiments, 2014 JINST 9 P07020
TWEPP 2015 - Topical Workshop on Electronics for Particle Physics,
September 28 - October 2, 2015, Instituto Superior Técnico, Lisbon, Portugal