MICROSYSTEMS LABORATORY
DEPARTMENT OF ELECTRICAL &
COMPUTER ENGINEERING
Microelectronic Hysteresis
Robert W. Newcomb
Talk for FICAMC: Plovdiv
August, 16, 2008
(Fifth International Conference of Applied Mathematics
and Computing – Bulgaria’2008)
2
The Old Town of Plovdiv by Ivan Theofilov
• Your ancient floors float among the stars.
Blue donkeys graze the silence around.
The Roman road leads down along matrimonial chandeliers.
A cry out of woman's flesh calls in the clock.
Violet-colored philistines go to bed in the deep houses,
they hear the pig, the hens, the train, the mouse.
The darkness dawns with quick sensual pupils.
The bridal veil flies away with the chimney's breath.
Blue donkeys run on the moonlit roofs.
Saints take off in a cloud from whitewashed churches,
with blood-soaked lambs they welcome the bridal veil.
Leopards gaze with amber eyes from the doorsteps.
Among box trees bacchantes with satin bands
pour fragrant myrrh out of bronze rhytons ...
Ivan Theofilov was born in Plovdiv in 1931 and graduated from the Theatre Academy in Sofia.
He is an honorary citizen of Plovdiv. The poem translated here is from Geometry of the Spirit,
published by Free Poetic Society, Sofia, 1996, and translated by Zdravka Mihaylova
3
Main topic of talk
The mathematics for the design of VLSI CMOS
circuits for hysteresis controlled by a voltage or current.
Possible uses:
Chaotic circuits, robust oscillators, memory,
debouncing, pixel holding, emulation of
chemical reactions, artificial neural networks,
buildings in earth quakes
Items for discussion:
Microlectronic hysteresis concept
The main idea, curve with movable load line
Representation via semistate equations
Key circuits used
Some examples
4
The concept for microelectronics
Hysteresis (ancient Greek = to lag behind)
a) Static: piecewise multi/single valued
[reason Spice won't run DC analysis on hysteresis]
along with
b) Dynamic: single valued given initial conditions
Typical (static):
binary
bent
5
Binary hysteresis curves
6
Example of use for holding pixels in presence of noise
7
Main Idea
Slide a load line, which depends upon the
hysteresis input parameter, across a nonlinear
function to give two or more intersections in
one region.
==>
8
CMOS circuit and bent V-I hysteresis
using inverters
9
CMOS bent hysteresis design curves
10
Designing all CMOS V-I hysteresis
11
CMOS inverter bent hysteresis
12
Hysteresis use in chaos generation
13
Multilevel hysteresis
14
Typical binary hysteresis circuit
OTA = operational transconductance amplifier
= voltage controlled current source
15
Variable hystereses
16
4 quadrant current mode hysteresis
17
Variable hysteresis from last circuit
18
Hysteresis in several dimensions
From UMCP dissertation of Yu Jiang
19
Circuit to realize 2D hysteresis
20
Dynamics via Semistate Equations
Edx/dt = A(x) + Bu
y = Cx
u = input, y = output, x = semistate
B, C, E constant matrices, E may be singular
A(x) nonlinear to generate hysteresis
21
Op-amp circuit for hysteresis
22
Semistate equations for op-amp example
kσ
v out  sσo (1 21(v )); 1(x)  unit step, s  d
d
dt
o
r
v  (1 r1 )(v  v )
out
d in
2
let u  v , x  vout , x  v ,
2 d
in 1
f(x)  (-1 2 1(x)), k  r /r then the semistate equations are
12 1 2
dx
1  σ x  kσ f(x )
o 1
o 2
dt
0  x  (1 k )x2  k u
1
12
12
yx
1
23
OTA circuit for hysteresis
24
OTA example semistate equations
i  I f(v )
out T d
d(v )
d  g(v  v )
i  Cgs
out
d in
dt
With v  x , i  x  y, v  u
d 1 out 2
in
the semistate equations are
dx
Cgs 1  g x  g u - x
1
2
dt
0  x  I f(x )
2 T 1
yx
2
25
OTA CMOS circuit
26
OTA curves
IT  epsI
1.1 10
4
8.8 10
5
6.6 10
5
4.4 10
5
2.2 10
5
iOTA( vd)
0
 IT  epsI
0
2.2 10
5
4.4 10
5
6.6 10
5
8.8 10
5
1.1 10
4
5
vdmin
gimax    2
IT

4
3
2
1
0
vd
1
2
3
4
vdmax
5
27
Sliding load line on OTA curve
1.1 10
4
8.8 10
5
6.6 10
5
iOTA ( vd)
0
4.4 10
5
igi[ go   ( 2 vi2( go) )  vd] 2.2 10
5
IT  epsI
igi( go   vi2( go)  vd)
0
igi( go  vi2( go)  vd)
2.2 10
5
igi( go  2 vi2( go)  vd)
4.4 10
5
6.6 10
5
8.8 10
5
1.1 10
4
 IT  epsI
5
vdmin
4
3
2
1
0
vd
1
Hysteresis for case of last curves. Uses two curves, upper & lower
2
3
4
vdmax
5
28
Resulting OTA hysteresis, Iout vs Vin
IT  epsI
hu( vi  go)
hl( vi  go)
 IT  epsI
1.1 10
4
8.8 10
5
6.6 10
5
4.4 10
5
2.2 10
5
2.2 10
5
4.4 10
5
6.6 10
5
8.8 10
5
1.1 10
4
0
5
vimin
4
3
2
1
0
vi
1
2
3
4
vimax
5
29
OTA VLSI layout
30
Neural type cell circuit
31
Neural type cell hysteresis
32
CMOS resistor from OTA
Floating resistor; can be
positive or negative
(by reversing green
Leads to M1 & M2)
M10
1
 
A 2 I adj K1, 2
M3 M4
M6
-Io(IR-)
Io(IR+)
M1 M2
V+
V-
M11
R 
M5
M7
M9
Vadj
1
A(Vadj  Vss ) 2 K1, 2 K 9
M8
33
PSpice Simulation: Positive Floating Resistor Circuit
• Observations
– Linear I-V region centered at V+ – V- = 0V
– IR+ and IR- show good symmetry
– Vadj modulates I-V linearity range
magnified
0.6
IR+
IR+, IR- [ A]
IR+, IR- [ A]
1.0
0.5
0.0
-3.4v
0.0
IR-
-0.3
-0.5
-1.0
-6.0
0.3
-4.0
-2.0
0.0
2.0
V+ – V- [V]
4.0
6.0
Vadj=
-2.4v
…
Vadj=
-3.4v
…
-2.4v
-0.6
-1.5
-0.75
0.0
V+ – V- [V]
0.75
1.5
34
dx  x3  (  ) x2  σ  x  k z
o
1 2
1 2
dt
dz  k x  k z  u
2
dt 1
for d(.)/dt  0:
z  ( 1 )x(x  σ )(x  σ )
1 ko
1
2
z  ( 1 )(k  u)
2
1
k
2
0.922
Plot for σ1=- σ2=1,
ko=1=k2=2k1
u3=0.136 at = slopes
Kinetic cells
1
0.9
0.8
0.7
0.6
0.5
z1( x)
0.4
0.3
0
0.2
z2( x  2 u3)
0.1
z2( x  u3)
0
0.1
z2( x u3)
0.2
z2( x 2 u3) 0.3
0.4
0.5
0.6
0.7
0.8
 0.922
0.9
1
1.3 1.13 0.95 0.78 0.61 0.43 0.26 0.08670.0867 0.26 0.43 0.61 0.78 0.95 1.13 1.3
xmin
x
xmax
Reference: V. Petrov, M. Peifer, J. Timmer, “Structural Stability Analysis of a Cell Cycle Control
Model,” Comptes rendus de l’Academie bulgare des Sciences, Tome 58, No. 1, 2005, pp. 19 – 24.
35
2
) /(2I
Circuit to give Iout=(Ix+Iy
w)
Subtract Ix2/(2Iw) &
Iy2/(2Iw)to get
I=IxIy/Iw
Iterate (= cascade
connections) to get
cubic, etc.
W. Gai, H. Chen, E. Seevinck, “Quadratic-translinear CMOS
Multiplier divider circuit,” Electronic Letters, May 1997, p. 860
36
Configuration to give cubic products
37
NPN differential pair
Apply differential voltage Vd and tail current Io then
Iout=I2-I1=Io·tanh(Vd/(2VT)), VT=thermal voltage=KT/Q
I2+I1=Io => 2·I2=Io(1+tanh(Vd/2VT)
2·I1=Io(1-tanh(Vd/2VT)
Multiplier via npn differential pair
Iout=(I4+I6)-(I3+I5)
=Io·tanh(Vx/2VT)tanh(Vy/2VT)
38
39
Cubic via npn differential pair:
Iout=Io·tanh(vx)tanh(vy)tanh(vz)
<=take diff=>
<=from previous=>
40
VLSI Transistors
Two basic types with two complementary of each:
MOSFET: NMOS & PMOS [piecewise square law]
BJT: npn & pnp [exponential law]
NMOS Law
For VGS ≤ Vth ID=0 off
For VGS>Vth
ID=(VGS-Vth)2
if VGS-VthVDS saturation
=(2(VGS-Vth)VDS-VDS2) if VGS-Vth<VDS Ohmic
=(Cox/2)(W/L)
If l ≠ 0 multiply by (1+lVDS); for now Vth>0
41
42
Useful CMOS current circuits
43
Setting up semistate equations
Use graph theory:
vb & ib = branch voltages and currents
vt & il = tree voltages and link (cotree) currents
KCL: 0t = Cib KVL: 0l= Tvb
==> vb = CTvt ib = TTil
ib=idevice+isource=id+is ; vb=vd+vs
by equivalences for devices id=Y(vd)
44
Useful equivalences
45
Example of setting up equations
Cutset equations = KCL at nodes I and II






0 1 0 1 1 0
i

i
;
ib

 i




in
 1b
0 0 1 0 1 1 b
i
i
i
i
2b 3b 4b 5b




T
46
Device characterization
0
i1d  

i   I (v ) 
D1 1
 2d  

 v1 
; v t   
i d  i 3d   
0
v2 
  


i 4d   sC(v1  v 2 ) 
i 5d  IS2 (v 2  Vdd )
0  i in  1 0 1 1 0
0   0   0 1 0  1 0i d 
  
 

0

i in   C  C  v1  

s

 0   C C   v  I (v )  I (v  V )
  
  2   D1 1
S2
2
dd 
47
Final semistate equations
0
 1
 1  1 dv t 
C

  i


 1 1  dt  I D1 (v1)  IS2 (v 2  Vdd ) 0 in
v
 1 0v
out
t
48
Idea of an extension
In terms of binary hysteresis can
set up a Preisach’s type of theory:
u
y(u)   w(x)dh(x)
uo
N
  w n h n (u)
n1
Where h is binary hysteresis and w is a weight
49
Alternate CMOS OTA hysteresis
50
CMOS OTAVout/Vin hysteresis circuit
51
Vout/Vin OTA hysteresis
VLSI Layout for 1.2U AMI fabrication
Vdd
Vr
52
6 main transistors
10ux10u, cap 38ux32u
Out
In
Vb
Gnd